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freescale semiconductor data sheet: advance information document number: mpc5646c rev. 3, may 2011 ? freescale semiconductor, inc., 2010, 2011. all rights reserved. preliminary?subject to change without notice this document contains information on a prod uct under development. freescale reserves the right to change or discontinue this product without notice. mpc5646c 176-pin lqfp (24 ? 24 mm) 208-pin lqfp (28 ? 28 mm) 256 mapbga (17 ? 17 mm) mpc5646c microcontroller data sheet ? e200z4d dual issue, 32-bit core power architecture ? compliant cpu ? up to 120 mhz ? 4 kb, 2/4-way set associ ative instruction cache ? variable length encoding (vle) ? embedded floating-point (fpu) unit ? supports nexus3+ ? e200z0h single issue, 32-bit core power architecture compliant cpu ? up to 80 mhz ? variable length encoding (vle) ? supports nexus3+ ? up to 3 mb on-chip flash memory: flash page buffers to improve access time ? up to 256 kb on-chip sram ? 64 kb on-chip data flash memory to support eeprom emulation ? up to 16 semaphores across all slave ports ? user selectable mbist ? low-power modes supported: stop, halt, standby ? 16 region memory protection unit (mpu) ? dual-core interrupt controller (intc). interrupt sources can be routed to e200z4d, e200z0h, or both ? frequency-modulated phas e-locked loop (fmpll) ? crossbar switch architectur e for concurrent access to peripherals, flash memory, and sram from multiple bus masters ? 32 channel edma controller with dmamux ? timer supports input/output channels providing 16-bit input capture, output compare, and pwm functions (emios) ? 2 analog-to-digital converters (adc): one 10-bit and one 12-bit ? cross trigger unit (ctu) to enable synchronization of adc conversions with a timer event from the emios or from the pit ? up to 8 serial peripher al interface (dspi) modules ? up to 10 serial communica tion interface (linflex) modules ? up to 6 full can (flexcan ) modules with 64 mbs each ? can sampler to catch id of can message ? 1 inter ic communication interface (i 2 c) module ? up to 177 (lqfp) or 199 (bga) configurable general purpose i/o pins ? system clocks sources ? 4?40 mhz external crystal oscillator ? 16 mhz internal rc oscillator ?fmpll additionally, there are two low power oscillators: 128 khz internal rc oscillator, 32 khz external crystal oscillator ? real time counter (rtc) with clock source from internal 128 khz or 16 mhz oscillators or external 4?40 mhz crystal ? supports autonomous wake-up with 1 ms resolution with max timeout of 2 seconds ? optional support from external 32 khz crystal oscillator, supporting wake-up with 1 second resolution and max timeout of 1 hour ? 1 system timer module (stm) with four 32-bit compare channels ? up to 8 periodic interrupt timers (pit) with 32-bit counter resolution ? 1 real time interrupt (rti) with 32-bit counter resolution ? 1 safety enhanced software watchdog timer (swt) that supports keyed functionality ? 1 dual-channel flexray controller with 128 message buffers ? 1 fast ethernet controller (fec) ? on-chip voltage regulator (vreg) ? cryptographic services engine (cse) ? offered in the following standard package types: ?176-pin lqfp, 24 ? 24 mm, 0.5 mm lead pitch ?208-pin lqfp, 28 ? 28 mm, 0.5 mm lead pitch ? 256-ball mapbga, 17 ? 17mm, 1.0 mm lead pitch www..net
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 2 table of contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.1 document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3 package pinouts and signal descriptions . . . . . . . . . . . . . . . . .9 3.1 pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.2 system pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 3.3 functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.1 parameter classification . . . . . . . . . . . . . . . . . . . . . . . .39 4.2 nvusro register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 4.2.1 nvusro [pad3v5v(0)] field description . . . . .40 4.2.2 nvusro [pad3v5v(1)] field description . . . . .40 4.3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . .40 4.4 recommended operating conditions . . . . . . . . . . . . . .42 4.5 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . .45 4.5.1 package thermal characteristics . . . . . . . . . . . .45 4.5.2 power considerations. . . . . . . . . . . . . . . . . . . . .45 4.6 i/o pad electrical characteristics . . . . . . . . . . . . . . . . . .46 4.6.1 i/o pad types . . . . . . . . . . . . . . . . . . . . . . . . . . .46 4.6.2 i/o input dc characteristics . . . . . . . . . . . . . . . .46 4.6.3 i/o output dc characteristics. . . . . . . . . . . . . . .47 4.6.4 output pin transition times . . . . . . . . . . . . . . . . .50 4.6.5 i/o pad current specification . . . . . . . . . . . . . . .51 4.7 reset electrical characteristics. . . . . . . . . . . . . . . . . .53 4.8 power management electrical characteristics. . . . . . . .55 4.8.1 voltage regulator electrical characteristics . . . .55 4.8.2 vdd_bv options . . . . . . . . . . . . . . . . . . . . . . . .56 4.8.3 voltage monitor electrical characteristics. . . . . .57 4.9 low voltage domain power consumption . . . . . . . . . . .58 4.10 flash memory electrical characteristics . . . . . . . . . . . .60 4.10.1 program/erase characteristics. . . . . . . . . . . . . .60 4.10.2 flash memory power supply dc characteristics62 4.10.3 flash memory start-up/switch-off timings . . . . .63 4.11 electromagnetic compatibility (emc) characteristics . .63 4.11.1 designing hardened software to avoid noise problems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4.11.2 electromagnetic interference (emi) . . . . . . . . . 64 4.11.3 absolute maximum ratings (electrical sensitivity)64 4.12 fast external crystal osci llator (4?40 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.13 slow external crystal os cillator (32 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 4.14 fmpll electrical characteristics . . . . . . . . . . . . . . . . . 70 4.15 fast internal rc oscillator (16 mhz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 4.16 slow internal rc oscill ator (128 khz) electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.17 adc electrical characteristics . . . . . . . . . . . . . . . . . . . 72 4.17.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 4.18 fast ethernet controller . . . . . . . . . . . . . . . . . . . . . . . 82 4.18.1 mii receive signal timing (rxd[3:0], rx_dv, rx_er, and rx_clk) . . . . . . . . . . . . . . . . . . . 82 4.18.2 mii transmit signal timing (txd[3:0], tx_en, tx_er, tx_clk) . . . . . . . . . . . . . . . . . . . . . . . 83 4.18.3 mii async inputs signal timing (crs and col)84 4.18.4 mii serial management channel timing (mdio and mdc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.19 on-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.19.1 current consumption . . . . . . . . . . . . . . . . . . . . 86 4.19.2 dspi characteristics. . . . . . . . . . . . . . . . . . . . . 88 4.19.3 nexus characteristics . . . . . . . . . . . . . . . . . . . . 96 4.19.4 jtag characteristics. . . . . . . . . . . . . . . . . . . . . 98 5 package characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 5.1 package mechanical data . . . . . . . . . . . . . . . . . . . . . 100 5.1.1 176 lqfp package mechanical drawing . . . . 100 5.1.2 208 lqfp package mechanical drawing . . . . 103 5.1.3 256 mapbga package mechanical drawing . 108 6 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 3 1 introduction 1.1 document overview this document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the mpc5646c device. to ensure a complete understanding of the device functionality, refer also to the mpc5646c reference manual. 1.2 description the mpc5646c is a new family of next generation microcontro llers built on the power architect ure embedded category. this document describes the features of the fa mily and options available within the family members, and highlights important electrical and physical char acteristics of the device. the mpc5646c family expands the range of the mpc560xb microcontroller family. it provides the scalability needed to implement platform approaches an d delivers the performance required by increas ingly sophisticated soft ware architectures. the advanced and cost-efficient host processor core of the mpc5646c automotive controller family complies with the power architecture embedded category, which is 100 percent user-mode compatible with the origin al power architecture user instruction set architectur e (uisa). it operates at speeds of up to 120 mhz and offers high performance processing optimized for low power consumption. it also cap italizes on the available development infr astructure of curren t power architecture devices and is supported with software drivers, operating system s and configuration code to assi st with users implementations.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 4 table 1. mpc5646c family comparison 1 feature MPC5644B mpc5644c mpc5645b mpc5645c mpc5646b mpc5646c package 176 lqfp 208 lqfp 176 lqfp 208 lqfp 256 bga 176 lqfp 208 lqfp 176 lqfp 208 lqfp 256 bga 176 lqfp 208 lqfp 176 lqfp 208 lqfp 256 bga cpu e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h e200z4d e200z4d + e200z0h execution speed 2 up to 120 mhz ( e200z4d ) up to 120 mhz ( e200z4d ) up to 80 mhz (e200z0h) 3 up to 120 mhz ( e200z4d ) up to 120 mhz ( e200z4d ) up to 80 mhz (e200z0h) 3 up to 120 mhz ( e200z4d ) up to 120 mhz ( e200z4d ) up to 80 mhz (e200z0h) 3 code flash memory 1.5 mb 2 mb 3 mb data flash memory 4 x16 kb sram 128 kb 192 kb 160 kb 256 kb 192 kb 256 kb mpu 16-entry edma 4 32 ch 10-bit adc 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch 27 ch 33 ch dedicated 5,6 shared with 12-bit adc 7 19 ch 12-bit adc 10 ch dedicated 8 shared with 10-bit adc 7 19 ch ctu 64 ch total timer i/o 9 emios 64 ch, 16-bit sci (linflexd) 10 spi (dspi) 8 can (flexcan) 10 6 flexray ye s stcu 11 ye s ethernet no yes no yes no yes i 2 c 1
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 5 32 khz oscillator (sxosc) yes gpio 12 147 177 147 177 199 147 177 147 177 199 147 177 147 177 199 debug jtag nexus 3+ jtag nexus 3+ jtag nexus 3+ cryptographic services engine (cse) optional 1 feature set dependent on selected peripheral multiplexing; table shows example. 2 based on 125 ? c ambient operating temperature and subj ect to full device characterisation. 3 the e200z0h can run at speeds up to 80 mhz. however, if system fr equency is >80 mhz (e.g., e200z4d running at 120 mhz) the e200z0h needs to run at 1/2 system frequency. th ere is a configurable e200z0 system clock di vider for this purpose. 4 dmamux also included that allows for software selection of 32 out of a possible 57 sources. 5 not shared with 12-bit adc, but possibl y shared with other alternate functions. 6 there are 23 dedicated ans plus 4 dedicat ed anx channels on lqpf176. for higher pi n count packages, there are 29 dedicated ans plus 4 dedicated anx channels. 7 16x precision channels (anp) and 3x standard (ans). 8 not shared with 10-bit adc, but possibl y shared with other alternate functions. 9 as a minimum, all timer channels can function as pwm or input ca pture and output control. refer to the emios section of the dev ice reference manual for information on the channel configuration and functions. 10 can sampler also included that allows id of can message to be captured when in low power mode. 11 stcu controls mbist activation and reporting. 12 estimated i/o count for proposed packages based on multiplexing with peripherals. table 1. mpc5646c family comparison 1 (continued) feature MPC5644B mpc5644c mpc5645b mpc5645c mpc5646b mpc5646c package 176 lqfp 208 lqfp 176 lqfp 208 lqfp 256 bga 176 lqfp 208 lqfp 176 lqfp 208 lqfp 256 bga 176 lqfp 208 lqfp 176 lqfp 208 lqfp 256 bga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 6 2 block diagram figure 1 shows the detailed block diagram of the mpc5646c. figure 1. mpc5646c block diagram 8 ? dspi fmpll nexus 3+ sram siul reset control 2 ? 128 kb external imux gpio & jtagc pad control jtag port nexus port e200z0h interrupt requests 64-bit 8 x 5 crossbar switch 6 ? flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi1 swt 8 ? 4 ? stm nmi1 intc i 2 c 10 ? linflexd 27 ch or 33 ch (2) mpu cmu 2 ? sram flash memory code flash 2 ? 1.5 mb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc/api sscm (master) (master) (slave) (slave) (slave) controller controller adc analog-to-digital converter bam boot assist module cse cryptographic services engine can controller area network (flexcan) cmu clock monitor unit ctu cross triggering unit dmamux dma channel multiplexer dspi deserial serial peripheral interface edma enhanced direct memory access flexcan controller area network controller modules fec fast ethenet controller emios enhanced modular input output system ecsm error correction status module fmpll frequency-modulated phase-locked loop flexray flexray communication controller i2c inter-integrated circuit bus imux internal multiplexer intc interrupt controller mpu ecsm from peripheral registers blocks emios e200z4d nexus 3+ nexus cse fec flexray wkpu 16 x semaphores stcu nmi0 nmi0 instructions (master) data (master) adc 1 ? 10-bit can sampler adc 10 ch (1) 1 ? 12-bit pit rti 2 ? 32 ch dmamux (3) (3) notes: 1) 10 dedicated channels plus up to 19 shared channels . see the device-comparison table. 2) package dependent. 27 or 33 dedicated channels plus up to 19 shared channels. see the device-comparison table. 3) (master) edma 16 x precision channels (anp) are mapped on input only i/o cells. jtagc jtag controller linflexd local interconnect network flexible with dma support mc_me mode entry module mc_cgm clock generation module mc_pcu power control unit mc_rgm reset generation module mpu memory protection unit nexus nexus development interface nmi non-maskable interrupt pit_rti periodic interrupt timer with real-time interrupt rtc/api real-time clock/ autonomous periodic interrupt siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer stcu self test control unit wkpu wakeup unit legend:
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 7 table 2 summarizes the functions of th e blocks present on the mpc5646c. table 2. mpc5646c series block summary block function analog-to-digital converter (adc) converts analog voltages to digital values boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit cryptographic security engine (cse) supports the encoding and decoding of any kind of data crossbar (xbar) switch supports simultaneous connections between two master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width dma channel multiplexer (dmamux) allows to route dma sources (called slots) to dma channels deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configurat ion and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors re ported by error-correcting codes enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ?n? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol fmpll (frequency-modulated phase-locked loop) generates high-speed system clocks and supports programmable frequency modulation flexray (flexray communication controller) provides high-speed distributed control for advanced automotive applications fast ethernet controller (fec) ethernet media access controller (mac) designed to support both 10 and 100 mbps ethernet/ieee 802.3 networks internal multiplexer (imux) siul subblock allows flexible mapping of peripheral interface on the different pins of the device inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests for both e200z0h and e200z4d cores jtag controller provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 8 linflexd (local interconnect network flexible with dma support) manages a high number of lin (local in terconnect network protocol) messages efficiently with a minimum of cpu load memory protection unit (mpu) provides hardware access control for all memory references generated in a device clock generation module (mc_cgm) provides logic and contro l required for the generatio n of system and peripheral clocks power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device mode entry module (mc_me) provides a mechanism for controlling the device operational mode and modetransition sequences in all functi onal states; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications non-maskable interrupt (nmi) handles external events t hat must produce an immediate response, such as power down detection nexus development interface (ndi) provides real-time development capab ilities for e200z0h and e200z4d core processor periodic interrupt timer/ real time interrupt timer (pit_rti) produces periodic interrupts and triggers real-time counter (rtc/api) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode). supports autonomous periodic interrupt (api) function to generate a periodic wakeup request to exit a low power mode or an interrupt request static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configurati on and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar and operating system tasks semaphores provides the hardware support needed in multi-core systems for sharing resources and provides a simple mechanism to achieve lock/unlock operations via a single write access. wake unit (wkpu) supports external sources that can generate interrupts or wakeup events, of which can cause non-maskable interrupt requests or wakeup events. table 2. mpc5646c series block summary (continued) block function
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 9 3 package pinouts and signal descriptions the available lqfp pinouts and the mapb ga ballmaps are provided in the following figures. for functional port pin description, see table 4 . figure 2. 176-pin lqfp configuration 176 lqfp top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pb[2] pc[8] pc[13] pc[12] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv_a vss_hv pc[1] ph[10] pa[6] pa[5] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa[4] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv_a pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv_a vss_hv pd[8] pb[4] pa[11] pa[10] pa[9] pa[8] pa[7] pe[13] pf[14] pf[15] vdd_hv_b vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa[3] pi[13] pi[12] pi[11] vdd_lv vss_lv pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv_a vss_hv ph[15] ph[13] ph[14] pi[6] pi[7] pg[5] pg[4] pg[3] pg[2] pa[2] pe[0] pa[1] pe[1] pe[8] pe[9] pep[10] a[0] pe[11] vss_hv vdd_hv_a vss_hv reset vss_lv vdd_lv vrc_ctrl pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] note 1) vdd_hv_b supplies the io voltage domain for the pins pe[12], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg[0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. 2)availability of port pin alternate functions depends on product selection.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 10 figure 3. 208-pin lqfp configuration 208 lqfp to p v i e w 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv_a vss_hv ph[15] ph[13] ph[14] p[i6] p[i7] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv_a vss_hv reset vss_lv vdd_lv vrc_ctrl pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pk[1] pk[2] pk[3] pk[4] pk[5] pk[6] pk[7] pk[8] pf[9] pf[8] pf[12] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv_b vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pi[13] pi[12] pi[11] pi[10] vdd_lv vss_lv pi[9] pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_a vss_hv pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pj[5] pj[6] pj[7] pj[8] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pj[12] pj[11] pa [ 4 ] pk[0] pj[15] pj[14] pj[13] pa[13] pj[10] pj[9] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv_a pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv_a vss_hv pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pl[0] pk[15] pk[14] pk[13] pk[12] pk[11] pk[10] pk[9] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv_a vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] note 1) vdd_hv_b supplies the io volt age domain for the pins pe[12], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg[0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. 2) availability of port pin alternat e functions depends on product selection.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a pc[15] pb[2] pc[13] pi[1] pe[7] ph[8] pe[2] pe[4] pc[4] pe[3] ph[9] pi[4] ph[11] pe[14] pa[10] pg[11] a b ph[13] pc[14] pc[8] pc[12] pi[3] pe[6] ph[5] pe[5] pc[ 5] pc[0] pc[2] ph[12] pg[10] pa[11] pa[9] pa[8] b c ph[14] vdd_hv _a pc[9] pl[0] pi[0] ph[7] ph[6] vss_lv vdd_hv _a pa[5] pc[3] pe[15] pg[14] pe[12] pa[7] pe[13] c d pg[5] pi[6] pj[4] pb[3] pk[15] pi[2] ph[4] vdd_lv pc[1] ph[10] pa[6] pi[5] pg[15] pf[14] pf[15] ph[2] d e pg[3] pi[7] ph[15] pg[2] pg[0] pg[1] ph[0] vdd_hv _a e f pa [ 2 ] p g [ 4 ] pa [ 1 ] p e [ 1 ] ph[1] ph[3] pg[12] pg[13] f g pe[8] pe[0] pe[10] pa[0] vss_hv vss_hv vss_hv vss_hv vdd_hv _b pi[13] pi[12] pa[3] g h pe[9] vdd_hv _a pe[11] pk[1] vss_lv vss_hv vss_hv vss_hv vdd_hv _a vdd_lv vss_lv pi[11] h j vss_hv vrc_ct rl vdd_lv pg[9] vss_lv vss_lv vss_hv vss_hv pd[15] pi[8] pi[9] pi[10] j k reset vss_lv pg[8] pc[11] vss_lv vss_lv vss_lv vdd_lv pd[14] pd[13] pb[14] pb[15] k l pc[10] pg[7] pb[0] pk[2] pd[12] pb[12] pb[13] vdd_hv _adc1 l m pg[6] pb[1] pk[4] pf[9] pb[11] pd[10] pd[11] vss_hv _adc1 m n pk[3] pf[8] pc[6] pc[7] pj[13] vdd_hv _a pb[10] pf[6] vdd_hv _a pj[1] pd[2] pj[5] pb[5] pb[6] pj[6] pd[9] n p pf[12] pf[10] pf[13] pa[14] pj[9] pa[12] pf[0] pf[5] pf[7] pj[3] pi[15] pd[4] pd[7] pd[8] pj[8] pj[7] p r pf[11] pa[15] pj[11] pj[15] pa[13] pf[2] pf[3] pf[4] vdd_lv pj[2] pj[0] pd[0] pd[3] pd[6] vdd_hv _adc0 pb[7] r t pj[12] pa[4] pk[0] pj[14] pj[10] pf[1] xtal extal vss_lv pb[9] pb[8] pi[14] pd[1] pd[5] vss_hv _adc0 pb[4] t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 notes: 1) vdd_hv_b supplies the io voltage domain for the pins pe[12 ], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg [0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. 2) availability of port pin alternat e functions depends on product selection.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 12 figure 4. 256-pin bga configuration 3.1 pad types in the device the following types of pads are avai lable for system pins and functional port pins: s = slow 1 m = medium 1, 2 12345678910111213141516 a pc[15] pb[2] pc[13] pi[1] pe[7] ph[8] pe[2] pe[4] pc[4] pe[3] ph[9] pi[4] ph[11] pe[14] pa[10] pg[11] a b ph[13] pc[14] pc[8] pc[12] pi[3] pe[6] ph[5] pe[5] pc[5] pc[0] pc[2] ph[12] pg[10] pa[11] pa[9] pa[8] b c ph[14] vdd_hv_ a pc[9] pl[0] pi[0] ph[7] ph[6] vss_lv vdd_hv_ a pa[5] pc[3] pe[15] pg[14] pe[12] pa[7] pe[13] c d pg[5] pi[6] pj[4] pb[3] pk[15] pi[2] ph[4] vdd_lv pc[1] ph[10] pa[6] pi[5] pg[15] pf[14] pf[15] ph[2] d e pg[3] pi[7] ph[15] pg[2] vdd_lv vss_lv pk[10] pk[9] pm[1] pm[0] pl[15] pl[14] pg[0] pg[1] ph[0] vdd_hv_ a e f pa[2] pg[4] pa[1] pe[1] pl[2] pm[6] pl[1] pk[11] pm[5] pl[13] pl[12] pm[2] ph[1] ph[3] pg[12] pg[13] f g pe[8] pe[0] pe[10] pa[0] pl[3] vss_hv vss_hv vss_hv vss_hv vss_hv vss_hv pk[12] vdd_hv_ b pi[13] pi[12] pa[3] g h pe[9] vdd_hv_ a pe[11] pk[1] pl[4] vss_lv vss_lv vss_hv vss_hv vss_hv vss_hv pk[13] vdd_hv_ a vdd_lv vss_lv pi[11] h j vss_hv vrc_ctr l vdd_lv pg[9] pl[5] vss_lv vss_lv vss_lv vss_hv vss_hv vss_hv pk[14] pd[15] pi[8] pi[9] pi[10] j k reset vss_lv pg[8] pc[11] pl[6] vss_lv vss_lv vss_lv vss_lv vdd_lv vdd_lv pm[3] pd[14] pd[13] pb[14] pb[15] k l pc[10] pg[7] pb[0] pk[2] pl[7] vss_lv vss_lv vss_lv vss_lv vdd_lv vdd_lv pm[4] pd[12] pb[12] pb[13] vdd_hv_ adc1 l m pg[6] pb[1] pk[4] pf[9] pk[5] pk[6] pk[7] pk[8] pl[8] pl[9] pl[10] pl[11] pb[11] pd[10] pd[11] vss_hv_ adc1 m n pk[3] pf[8] pc[6] pc[7] pj[13] vdd_hv_ a pb[10] pf[6] vdd_hv_ a pj[1] pd[2] pj[5] pb[5] pb[6] pj[6] pd[9] n p pf[12] pf[10] pf[13] pa[14] pj[9] pa[12] pf[0] pf[5 ] pf[7] pj[3] pi[15] pd[4] pd[7] pd[8] pj[8] pj[7] p r pf[11] pa[15] pj[11] pj[15] pa[13] pf[2] pf[3] pf [4] vdd_lv pj[2] pj[0] pd[0] pd[3] pd[6] vdd_hv_ adc0 pb[7] r t pj[12] pa[4] pk[0] pj[14] pj[10] pf[1] xtal extal vss_lv pb[9] pb[8] pi[14] pd[1] pd[5] vss_hv_ adc0 pb[4] t 12345678910111213141516 notes: 1) vdd_hv_b supplies the io voltage domain for the pins pe[12], pa[11], pa[10], pa[9], pa[8], pa[7], pe[13], pf[14], pf[15], pg [0], pg[1], ph[3], ph[2], ph[1], ph[0], pg[12], pg[13], and pa[3]. 2)availability of port pin alternat e functions depends on product selection. 1. see the i/o pad electrical characteristics in the device data sheet for details. 2. all medium and fast pads are in slow configuration by default at reset and can be configured as fast or medium. for example, fast/medium pad will be medium by default at reset. similarly, slow/medium pad will be slow by default. only exception is pc[1] which is in medium configuration by default (refer to p cr.src in the reference manual, pad configuration registers (pcr0?pcr198)).
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 13 f = fast 1, 2 i = input only with analog feature 1 a = analog 3.2 system pins the system pins are listed in table 3 . 3.3 functional ports the functional port pins are listed in table 4 . table 3. system pin descriptions port pin function i/o direction pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga reset bidirectional reset with schmitt-trigger characteristics and noise filter. i/o m input, weak pull-up only after phase2 29 29 k1 extal analog output of the oscillator amplifier circuit, when the oscillator is not in bypass mode. analog input for the clock generator when the oscillator is in bypass mode. i/o a 1 1 for analog pads, it is not recommended to enable ibe if apc is enabled to avoid extra current in middle range voltage. ?5874t8 xtal analog input of the oscillator amplifier circuit. needs to be grounded if oscillator bypass mode is used. ia 1 ?5672t7 table 4. functional port pin descriptions port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga pa[0] pcr[0] af0 af1 af2 af3 ? ? gpio[0] e0uc[0] clkout e0uc[13] wkpu[19] can1rx siul emios_0 mc_cgm emios_0 wkpu flexcan_1 i/o i/o o i/o i i m/s tristate 24 24 g4
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 14 pa[1] pcr[1] af0 af1 af2 af3 ? ? ? gpio[1] e0uc[1] ? ? wkpu[2] can3rx nmi[0] 3 siul emios_0 ? ? wkpu flexcan_3 wkpu i/o i/o ? ? i i i s tristate 19 19 f3 pa[2] pcr[2] af0 af1 af2 af3 ? ? gpio[2] e0uc[2] ? ma[2] wkpu[3] nmi[1] 3 siul emios_0 ? adc_0 wkpu wkpu i/o i/o ? o i i s tristate 17 17 f1 pa[3] pcr[3] af0 af1 af2 af3 ? ? ? gpio[3] e0uc[3] lin5tx cs4_1 rx_er_clk eirq[0] adc1_s[0] siul emios_0 linflexd_5 dspi_1 fec siul adc_1 i/o i/o o o i i i m/s tristate 114 138 g16 pa[4] pcr[4] af0 af1 af2 af3 ? ? gpio[4] e0uc[4] ? cs0_1 lin5rx wkpu[9] siul emios_0 ? dspi_1 linflexd_5 wkpu i/o i/o ? i/o i i s tristate 51 61 t2 pa[5] pcr[5] af0 af1 af2 gpio[5] e0uc[5] lin4tx siul emios_0 linflexd_4 i/o i/o o m/s tristate 146 170 c10 pa[6] pcr[6] af0 af1 af2 af3 ? ? gpio[6] e0uc[6] ? cs1_1 lin4rx eirq[1] siul emios_0 ? dspi_1 linflexd_4 siul i/o i/o ? o i i s tristate 147 171 d11 pa[7] pcr[7] af0 af1 af2 af3 ? ? ? gpio[7] e0uc[7] lin3tx ? rxd[2] eirq[2] adc1_s[1] siul emios_0 linflexd_3 ? fec siul adc_1 i/o i/o o ? i i i m/s tristate 128 152 c15 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 15 pa[8] pcr[8] af0 af1 af2 af3 ? ? ? ? gpio[8] e0uc[8] e0uc[14] ? rxd[1] eirq[3] abs[0] lin3rx siul emios_0 emios_0 ? fec siul mc_rgm linflexd_3 i/o i/o i/o ? i i i i m/s input, weak pull-up 129 153 b16 pa[9] pcr[9] af0 af1 af2 af3 ? ? gpio[9] e0uc[9] ? cs2_1 rxd[0] fab siul emios_0 ? dspi1 fec mc_rgm i/o i/o ? o i i m/s pull- down 130 154 b15 pa[10] pcr[10] af0 af1 af2 af3 ? ? ? gpio[10] e0uc[10] sda lin2tx col adc1_s[2] sin_1 siul emios_0 i 2 c linflexd_2 fec adc_1 dspi_1 i/o i/o i/o o i i i m/s tristate 131 155 a15 pa[11] pcr[11] af0 af1 af2 af3 ? ? ? ? gpio[11] e0uc[11] scl ? rx_er eirq[16] lin2rx adc1_s[3] siul emios_0 i 2 c ? fec siul linflexd_2 adc_1 i/o i/o i/o ? i i i i m/s tristate 132 156 b14 pa[12] pcr[12] af0 af1 af2 af3 ? ? gpio[12] ? e0uc[28] cs3_1 eirq[17] sin_0 siul ? emios_0 dspi1 siul dspi_0 i/o ? i/o o i i s tristate 53 69 p6 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 e0uc[29] ? siul dspi_0 emios_0 ? i/o o i/o ? m/s tristate 52 66 r5 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i m/s tristate 50 58 p4 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 16 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkpu[10] siul dspi_0 dspi_0 emios_0 wkpu i/o i/o i/o i/o i m/s tristate 48 56 r2 pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx e0uc[30] lin0tx siul flexcan_0 emios_0 linflexd_0 i/o o i/o i m/s tristate 39 39 l3 pb[1] pcr[17] af0 af1 af2 ? ? ? gpio[17] ? e0uc[31] lin0rx wkpu[4] can0rx siul ? emios_0 linflexd_0 wkpu flexcan_0 i/o ? i/o i i i s tristate 40 40 m2 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda e0uc[30] siul linflexd_0 i 2 c emios_0 i/o o i/o i/o m/s tristate 176 208 a2 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] e0uc[31] scl ? wkpu[11] lin0rx siul emios_0 i 2 c ? wkpu linflexd_0 i/o i/o i/o ? i i s tristate 1 1 d4 pb[4] pcr[20] af0 af1 af2 af3 ? ? gpi[20] ? ? ? adc0_p[0] adc1_p[0] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 88 104 t16 pb[5] pcr[21] af0 af1 af2 af3 ? ? gpi[21] ? ? ? adc0_p[1] adc1_p[1] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 91 107 n13 pb[6] pcr[22] af0 af1 af2 af3 ? ? gpi[22] ? ? ? adc0_p[2] adc1_p[2] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 92 108 n14 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 17 pb[7] pcr[23] af0 af1 af2 af3 ? ? gpi[23] ? ? ? adc0_p[3] adc1_p[3] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 93 109 r16 pb[8] pcr[24] af0 af1 af2 af3 ? ? ? ? gpi[24] ? ? ? adc0_s[0] adc1_s[4] wkpu[25] osc32k_xtal 4 siul ? ? ? adc_0 adc_1 wkpu sxosc i ? ? ? i i i i i ? 61 77 t11 pb[9] 5 pcr[25] af0 af1 af2 af3 ? ? ? ? gpi[25] ? ? ? adc0_s[1] adc1_s[5] wkpu[26] osc32k_extal 4 siul ? ? ? adc_0 adc_1 wkpu sxosc i ? ? ? i i i i i ? 60 76 t10 pb[10] pcr[26] af0 af1 af2 af3 ? ? ? gpio[26] sout_1 can3tx ? adc0_s[2] adc1_s[6] wkpu[8] siul dspi_1 flexcan_3 ? adc_0 adc_1 wkpu i/o o ? ? i i i s tristate 62 78 n7 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc0_s[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? i/o i s tristate 97 117 m13 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc0_x[0] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 101 123 l14 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc0_x[1] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 103 125 l15 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 18 pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc0_x[2] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 105 127 k15 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc0_x[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i s tristate 107 129 k16 pc[0] 6 pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m/s input, weak pull-up 154 178 b10 pc[1] 6 pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f/m tristate 149 173 d9 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx ? eirq[5] siul dspi_1 flexcan_4 ? siul i/o i/o o ? i m/s tristate 145 169 b11 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] ? can1rx can4rx eirq[6] siul dspi_1 adc_0 ? flexcan_1 flexcan_4 siul i/o i/o o i i i s tristate 144 168 c11 pc[4] pcr[36] af0 af1 af2 af3 alt4 ? ? ? gpio[36] e1uc[31] ? fr_b_tx_en sin_1 can3rx eirq[18] siul emios_1 ? flexray dspi_1 flexcan_3 siul i/o i/o ? o i i i m/s tristate 159 183 a9 pc[5] pcr[37] af0 af1 af2 af3 alt4 ? gpio[37] sout_1 can3tx ? fr_a_tx eirq[7] siul dspi_1 flexcan_3 ? flexray siul i/o o o ? o i m/s tristate 158 182 b9 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 19 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx e1uc[28] ? siul linflexd_1 emios_1 ? i/o o i/o ? s tristate 44 52 n3 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? e1uc[29] ? lin1rx wkpu[12] siul ? emios_1 ? linflexd_1 wkpu i/o ? i/o ? i i s tristate 45 53 n4 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx e0uc[3] ? siul linflexd_2 emios_0 ? i/o o i/o ? s tristate 175 207 b3 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? e0uc[7] ? lin2rx wkpu[13] siul ? emios_0 ? linflexd_2 wkpu i/o ? i/o ? i i s tristate 2 2 c3 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx ma[1] siul flexcan_1 flexcan_4 adc_0 i/o o o o m/s tristate 36 36 l1 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ma[2] can1rx can4rx wkpu[5] siul ? ? adc_0 flexcan_1 flexcan_4 wkpu i/o ? ? o i i i s tristate 35 35 k4 pc[12] pcr[44] af0 af1 af2 af3 alt4 ? ? gpio[44] e0uc[12] ? ? fr_dbg[0] sin_2 eirq[19] siul emios_0 ? ? flexray dspi_2 siul i/o i/o ? ? o i i m/s tristate 173 205 b4 pc[13] pcr[45] af0 af1 af2 af3 alt4 gpio[45] e0uc[13] sout_2 ? fr_dbg[1] siul emios_0 dspi_2 ? flexray i/o i/o o ? o m/s tristate 174 206 a3 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 20 pc[14] pcr[46] af0 af1 af2 af3 alt4 ? gpio[46] e0uc[14] sck_2 ? fr_dbg[2] eirq[8] siul emios_0 dspi_2 ? flexray siul i/o i/o i/o ? o i m/s tristate 3 3 b2 pc[15] pcr[47] af0 af1 af2 af3 alt4 gpio[47] e0uc[15] cs0_2 ? fr_dbg[3] eirq[20] siul emios_0 dspi_2 ? flexray siul i/o i/o i/o ? o i m/s tristate 4 4 a1 pd[0] pcr[48] af0 af1 af2 af3 ? ? ? gpi[48] ? ? ? adc0_p[4] adc1_p[4] wkpu[27] siul ? ? ? adc_0 adc_1 wkpu i ? ? ? i i i itristate 77 93 r12 pd[1] pcr[49] af0 af1 af2 af3 ? ? ? gpi[49] ? ? ? adc0_p[5] adc1_p[5] wkpu[28] siul ? ? ? adc_0 adc_1 wkpu i ? ? ? i i i itristate 78 94 t13 pd[2] pcr[50] af0 af1 af2 af3 ? ? gpi[50] ? ? ? adc0_p[6] adc1_p[6] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 79 95 n11 pd[3] pcr[51] af0 af1 af2 af3 ? ? gpi[51] ? ? ? adc0_p[7] adc1_p[7] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 80 96 r13 pd[4] pcr[52] af0 af1 af2 af3 ? ? gpi[52] ? ? ? adc0_p[8] adc1_p[8] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 81 97 p12 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 21 pd[5] pcr[53] af0 af1 af2 af3 ? ? gpi[53] ? ? ? adc0_p[9] adc1_p[9] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 82 98 t14 pd[6] pcr[54] af0 af1 af2 af3 ? ? gpi[54] ? ? ? adc0_p[10] adc1_p[10] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate 83 99 r14 pd[7] pcr[55] af0 af1 af2 af3 ? ? gpi[55] ? ? ? adc0_p[11] adc1_p[11] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 84 100 p13 pd[8] pcr[56] af0 af1 af2 af3 ? ? gpi[56] ? ? ? adc0_p[12] adc1_p[12] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 87 103 p14 pd[9] pcr[57] af0 af1 af2 af3 ? ? gpi[57] ? ? ? adc0_p[13] adc1_p[13] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 94 114 n16 pd[10] pcr[58] af0 af1 af2 af3 ? ? gpi[58] ? ? ? adc0_p[14] adc1_p[14] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 95 115 m14 pd[11] pcr[59] af0 af1 af2 af3 ? ? gpi[59] ? ? ? adc0_p[15] adc1_p[15] siul ? ? ? adc_0 adc_1 i ? ? ? i i i tristate 96 116 m15 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 22 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc0_s[4] siul dspi_0 emios_0 ? adc_0 i/o o i/o ? i s tristate 100 120 l13 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc0_s[5] siul dspi_1 emios_0 ? adc_0 i/o i/o i/o ? i s tristate 102 124 k14 pd[14] pcr[62] af0 af1 af2 af3 alt4 ? gpio[62] cs1_1 e0uc[26] ? fr_dbg[0] adc0_s[6] siul dspi_1 emios_0 ? flexray adc_0 i/o o i/o ? o i s tristate 104 126 k13 pd[15] pcr[63] af0 af1 af2 af3 alt4 ? gpio[63] cs2_1 e0uc[27] ? fr_dbg[1] adc0_s[7] siul dspi_1 emios_0 ? flexray adc_0 i/o o i/o ? o i s tristate 106 128 j13 pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? can5rx wkpu[6] siul emios_0 ? ? flexcan_5 wkpu i/o i/o ? ? i i s tristate 18 18 g2 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx ? siul emios_0 flexcan_5 ? i/o i/o o ? m/s tristate 20 20 f4 pe[2] pcr[66] af0 af1 af2 af3 alt4 ? ? gpio[66] e0uc[18] ? ? fr_a_tx_en sin_1 eirq[21] siul emios_0 ? ? flexray dspi_1 siul i/o i/o ? ? o i i m/s tristate 156 180 a7 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 23 pe[3] pcr[67] af0 af1 af2 af3 ? ? gpio[67] e0uc[19] sout_1 ? fr_a_rx wkpu[29] siul emios_0 dspi_1 ? flexray wkpu i/o i/o o ? i i m/s tristate 157 181 a10 pe[4] pcr[68] af0 af1 af2 af3 alt4 ? gpio[68] e0uc[20] sck_1 ? fr_b_tx eirq[9] siul emios_0 dspi_1 ? flexray siul i/o i/o i/o ? o i m/s tristate 160 184 a8 pe[5] pcr[69] af0 af1 af2 af3 ? ? gpio[69] e0uc[21] cs0_1 ma[2] fr_b_rx wkpu[30] siul emios_0 dspi_1 adc_0 flexray wkpu i/o i/o i/o o i i m/s tristate 161 185 b8 pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[22] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m/s tristate 167 191 b6 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[23] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m/s tristate 168 192 a5 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx e0uc[22] can3tx siul flexcan_2 emios_0 flexcan_3 i/o o i/o o m/s tristate 21 21 g1 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkpu[7] can2rx can3rx siul ? emios_0 ? wkpu flexcan_2 flexcan_3 i/o ? i/o ? i i i s tristate 22 22 h1 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 e1uc[30] eirq[10] siul linflexd_3 dspi_1 emios_1 siul i/o o o i/o i s tristate 23 23 g3 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 24 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] e0uc[24] cs4_1 ? lin3rx wkpu[14] siul emios_0 dspi_1 ? linflexd_3 wkpu i/o i/o o ? i i s tristate 25 25 h3 pe[12] pcr[76] af0 af1 af2 af3 ? ? ? ? gpio[76] ? e1uc[19] ? crs sin_2 eirq[11] adc1_s[7] siul ? emios_1 ? fec dspi_2 siul adc_1 i/o ? i/o ? i i i i m/s tristate 133 157 c14 pe[13] pcr[77] af0 af1 af2 af3 ? gpio[77] sout_2 e1uc[20] ? rxd[3] siul dspi_2 emios_1 ? fec i/o o i/o ? i m/s tristate 127 151 c16 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i m/s tristate 136 160 a14 pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] sck_6 siul dspi_2 emios_1 dspi_6 i/o i/o i/o i/o m/s tristate 137 161 c12 pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? adc0_s[8] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i s tristate 63 79 p7 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? adc0_s[9] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i s tristate 64 80 t6 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? adc0_s[10] siul emios_0 dspi_2 ? adc_0 i/o i/o i/o ? i s tristate 65 81 r6 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 25 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? adc0_s[11] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i s tristate 66 82 r7 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? adc0_s[12] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i s tristate 67 83 r8 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? adc0_s[13] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i s tristate 68 84 p8 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] cs1_1 ? adc0_s[14] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i s tristate 69 85 n8 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? cs2_1 ? adc0_s[15] siul ? dspi_1 ? adc_0 i/o ? o ? i s tristate 70 86 p9 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx cs4_0 can2tx siul flexcan_3 dspi_0 flexcan_2 i/o o o o m/s tristate 42 50 n2 pf[9] pcr[89] af0 af1 af2 af3 ? ? ? gpio[89] e1uc[1] cs5_0 ? can2rx can3rx wkpu[22] siul emios_1 dspi_0 ? flexcan_2 flexcan_3 wkpu i/o i/o o ? i i i s tristate 41 49 m4 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] cs1_0 lin4tx e1uc[2] siul dspi_0 linflexd_4 emios_1 i/o o o i/o m/s tristate 46 54 p2 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 26 pf[11] pcr[91] af0 af1 af2 af3 ? ? gpio[91] cs2_0 e1uc[3] ? lin4rx wkpu[15] siul dspi_0 emios_1 ? linflexd_4 wkpu i/o o i/o ? i i s tristate 47 55 r1 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] lin5tx ? siul emios_1 linflexd_5 ? i/o i/o o ? m/s tristate 43 51 p1 pf[13] pcr[93] af0 af1 af2 af3 ? ? gpio[93] e1uc[26] ? ? lin5rx wkpu[16] siul emios_1 ? ? linflexd_5 wkpu i/o i/o ? ? i i s tristate 49 57 p3 pf[14] pcr[94] af0 af1 af2 af3 alt4 gpio[94] can4tx e1uc[27] can1tx mdio siul flexcan_4 emios_1 flexcan_1 fec i/o o i/o o i/o m/s tristate 126 150 d14 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? ? gpio[95] e1uc[4] ? ? rx_dv can1rx can4rx eirq[13] siul emios_1 ? ? fec flexcan_1 flexcan_4 siul i/o i/o ? ? i i i i m/s tristate 125 149 d15 pg[0] pcr[96] af0 af1 af2 af3 alt4 gpio[96] can5tx e1uc[23] ? mdc siul flexcan_5 emios_1 ? fec i/o o i/o ? o f tristate 122 146 e13 pg[1] pcr[97] af0 af1 af2 af3 ? ? ? gpio[97] ? e1uc[24] ? tx_clk can5rx eirq[14] siul ? emios_1 ? fec flexcan_5 siul i/o ? i/o ? i i i m tristate 121 145 e14 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 27 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] sout_3 ? siul emios_1 dspi_3 ? i/o i/o o ? m/s tristate 16 16 e4 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] cs0_3 ? wkpu[17] siul emios_1 dspi_3 ? wkpu i/o i/o i/o ? i s tristate 15 15 e1 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] sck_3 ? siul emios_1 dspi_3 ? i/o i/o i/o ? m/s tristate 14 14 f2 pg[5] pcr[101] af0 af1 af2 af3 ? ? gpio[101] e1uc[14] ? ? wkpu[18] sin_3 siul emios_1 ? ? wkpu dspi_3 i/o i/o ? ? i i s tristate 13 13 d1 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] lin6tx ? siul emios_1 linflexd_6 ? i/o i/o o ? m/s tristate 38 38 m1 pg[7] pcr[103] af0 af1 af2 af3 ? ? gpio[103] e1uc[16] e1uc[30] ? lin6rx wkpu[20] siul emios_1 emios_1 ? linflexd_6 wkpu i/o i/o i/o ? i i s tristate 37 37 l2 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] lin7tx cs0_2 eirq[15] siul emios_1 linflexd_7 dspi_2 siul i/o i/o o i/o i s tristate 34 34 k3 pg[9] pcr[105] af0 af1 af2 af3 ? ? gpio[105] e1uc[18] ? sck_2 lin7rx wkpu[21] siul emios_1 ? dspi_2 linflexd_7 wkpu i/o i/o ? i/o i i s tristate 33 33 j4 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 28 pg[10] pcr[106] af0 af1 af2 af3 ? gpio[106] e0uc[24] e1uc[31] ? sin_4 siul emios_0 emios_1 ? dspi_4 i/o i/o i/o ? i s tristate 138 162 b13 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] cs0_4 cs0_6 siul emios_0 dspi_4 dspi_6 i/o i/o i/o i/o m/s tristate 139 163 a16 pg[12] pcr[108] af0 af1 af2 af3 alt4 gpio[108] e0uc[26] sout_4 ? txd[2] siul emios_0 dspi_4 ? fec i/o i/o o ? o m/s tristate 116 140 f15 pg[13] pcr[109] af0 af1 af2 af3 alt4 gpio[109] e0uc[27] sck_4 ? txd[3] siul emios_0 dspi_4 ? fec i/o i/o i/o ? o m/s tristate 115 139 f16 pg[14] pcr[110] af0 af1 af2 af3 ? gpio[110] e1uc[0] lin8tx ? sin_6 siul emios_1 linflexd_8 ? dspi_6 i/o i/o o ? i s tristate 134 158 c13 pg[15] pcr[111] af0 af1 af2 af3 ? gpio[111] e1uc[1] sout_6 ? lin8rx siul emios_1 dspi_6 ? linflexd_8 i/o i/o o ? i m/s tristate 135 159 d13 ph[0] pcr[112] af0 af1 af2 af3 alt4 ? gpio[112] e1uc[2] ? ? txd[1] sin_1 siul emios_1 ? ? fec dspi_1 i/o i/o ? ? o i m/s tristate 117 141 e15 ph[1] pcr[113] af0 af1 af2 af3 alt4 gpio[113] e1uc[3] sout_1 ? txd[0] siul emios_1 dspi_1 ? fec i/o i/o o ? o m/s tristate 118 142 f13 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 29 ph[2] pcr[114] af0 af1 af2 af3 alt4 gpio[114] e1uc[4] sck_1 ? tx_en siul emios_1 dspi_1 ? fec i/o i/o i/o ? o m/s tristate 119 143 d16 ph[3] pcr[115] af0 af1 af2 af3 alt4 gpio[115] e1uc[5] cs0_1 ? tx_er siul emios_1 dspi_1 ? fec i/o i/o i/o ? o m/s tristate 120 144 f14 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] sout_7 ? siul emios_1 dspi_7 ? i/o i/o o ? m/s tristate 162 186 d7 ph[5] pcr[117] af0 af1 af2 af3 ? gpio[117] e1uc[7] ? ? sin_7 siul emios_1 ? ? dspi_7 i/o i/o ? ? i s tristate 163 187 b7 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] sck_7 ma[2] siul emios_1 dspi_7 adc_0 i/o i/o i/o o m/s tristate 164 188 c7 ph[7] pcr[119] af0 af1 af2 af3 alt4 gpio[119] e1uc[9] cs3_2 ma[1] cs0_7 siul emios_1 dspi_2 adc_0 dspi_7 i/o i/o o o i/o m/s tristate 165 189 c6 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc_0 i/o i/o o o m/s tristate 166 190 a6 ph[9] 6 pcr[121] af0 af1 af2 af3 ? gpio[121] ? ? ? tck siul ? ? ? jtagc i/o ? ? ? i s input, weak pull-up 155 179 a11 ph[10] 6 pcr[122] af0 af1 af2 af3 ? gpio[122] ? ? ? tms siul ? ? ? jtagc i/o ? ? ? i m/s input, weak pull-up 148 172 d10 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 30 ph[11] pcr[123] af0 af1 af2 af3 gpio[123] sout_3 cs0_4 e1uc[5] siul dspi_3 dspi_4 emios_1 i/o o i/o i/o m/s tristate 140 164 a13 ph[12] pcr[124] af0 af1 af2 af3 gpio[124] sck_3 cs1_4 e1uc[25] siul dspi_3 dspi_4 emios_1 i/o i/o o i/o m/s tristate 141 165 b12 ph[13] pcr[125] af0 af1 af2 af3 gpio[125] sout_4 cs0_3 e1uc[26] siul dspi_4 dspi_3 emios_1 i/o o i/o i/o m/s tristate 9 9 b1 ph[14] pcr[126] af0 af1 af2 af3 gpio[126] sck_4 cs1_3 e1uc[27] siul dspi_4 dspi_3 emios_1 i/o i/o o i/o m/s tristate 10 10 c1 ph[15] pcr[127] af0 af1 af2 af3 gpio[127] sout_5 ? e1uc[17] siul dspi_5 ? emios_1 i/o o ? i/o m/s tristate 8 8 e3 pi[0] pcr[128] af0 af1 af2 af3 gpio[128] e0uc[28] lin8tx ? siul emios_0 linflexd_8 ? i/o i/o o ? s tristate 172 196 c5 pi[1] pcr[129] af0 af1 af2 af3 ? ? gpio[129] e0uc[29] ? ? wkpu[24] lin8rx siul emios_0 ? ? wkpu linflexd_8 i/o i/o ? ? i i s tristate 171 195 a4 pi[2] pcr[130] af0 af1 af2 af3 gpio[130] e0uc[30] lin9tx ? siul emios_0 linflexd_9 ? i/o i/o o ? s tristate 170 194 d6 pi[3] pcr[131] af0 af1 af2 af3 ? ? gpio[131] e0uc[31] ? ? wkpu[23] lin9rx siul emios_0 ? ? wkpu linflexd_9 i/o i/o ? ? i i s tristate 169 193 b5 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 31 pi[4] pcr[132] af0 af1 af2 af3 gpio[132] e1uc[28] sout_4 ? siul emios_1 dspi_4 ? i/o i/o o ? m/s tristate 143 167 a12 pi[5] pcr[133] af0 af1 af2 af3 alt4 gpio[133] e1uc[29] sck_4 cs2_5 cs2_6 siul emios_1 dspi_4 dspi_5 dspi_6 i/o i/o i/o o o m/s tristate 142 166 d12 pi[6] pcr[134] af0 af1 af2 af3 alt4 gpio[134] e1uc[30] cs0_4 cs0_5 cs0_6 siul emios_1 dspi_4 dspi_5 dspi_6 i/o i/o i/o i/o i/o s tristate 11 11 d2 pi[7] pcr[135] af0 af1 af2 af3 alt4 gpio[135] e1uc[31] cs1_4 cs1_5 cs1_6 siul emios_1 dspi_4 dspi_5 dspi_6 i/o i/o o o o s tristate 12 12 e2 pi[8] pcr[136] af0 af1 af2 af3 ? gpio[136] ? ? ? adc0_s[16] siul ? ? ? adc_0 i/o ? ? ? i s tristate 108 130 j14 pi[9] pcr[137] af0 af1 af2 af3 ? gpio[137] ? ? ? adc0_s[17] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 131 j15 pi[10] pcr[138] af0 af1 af2 af3 ? gpio[138] ? ? ? adc0_s[18] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 134 j16 pi[11] pcr[139] af0 af1 af2 af3 ? ? gpio[139] ? ? ? adc0_s[19] sin_3 siul ? ? ? adc_0 dspi_3 i/o ? ? ? i i s tristate 111 135 h16 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 32 pi[12] pcr[140] af0 af1 af2 af3 ? gpio[140] cs0_3 cs0_2 ? adc0_s[20] siul dspi_3 dspi_2 ? adc_0 i/o i/o i/o ? i s tristate 112 136 g15 pi[13] pcr[141] af0 af1 af2 af3 ? gpio[141] cs1_3 cs1_2 ? adc0_s[21] siul dspi_3 dspi_2 ? adc_0 i/o o o ? i s tristate 113 137 g14 pi[14] pcr[142] af0 af1 af2 af3 ? ? gpio[142] ? ? ? adc0_s[22] sin_4 siul ? ? ? adc_0 dspi_4 i/o ? ? ? i i stristate 76 92 t12 pi[15] pcr[143] af0 af1 af2 af3 ? gpio[143] cs0_4 cs2_2 ? adc0_s[23] siul dspi_4 dspi_2 ? adc_0 i/o i/o o ? i stristate 75 91 p11 pj[0] pcr[144] af0 af1 af2 af3 ? gpio[144] cs1_4 cs3_2 ? adc0_s[24] siul dspi_4 dspi_2 ? adc_0 i/o o o ? i stristate 74 90 r11 pj[1] pcr[145] af0 af1 af2 af3 ? ? gpio[145] ? ? ? adc0_s[25] sin_5 siul ? ? ?? adc_0 dspi_5 i/o ? ? ? i i stristate 73 89 n10 pj[2] pcr[146] af0 af1 af2 af3 ? gpio[146] cs0_5 cs0_6 cs0_7 adc0_s[26] siul dspi_5 dspi_6 dspi_7 adc_0 i/o i/o i/o i/o i stristate 72 88 r10 pj[3] pcr[147] af0 af1 af2 af3 ? gpio[147] cs1_5 cs1_6 cs1_7 adc0_s[27] siul dspi_5 dspi_6 dspi_7 adc_0 i/o o o o i stristate 71 87 p10 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 33 pj[4] pcr[148] af0 af1 af2 af3 gpio[148] sck_5 e1uc[18] ? siul dspi_5 emios_1 ? i/o i/o i/o ? m/s tristate 5 5 d3 pj[5] pcr[149] af0 af1 af2 af3 ? gpio[149] ? ? ? adc0_s[28] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 113 n12 pj[6] pcr[150] af0 af1 af2 af3 ? gpio[150] ? ? ? adc0_s[29] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 112 n15 pj[7] pcr[151] af0 af1 af2 af3 ? gpio[151] ? ? ? adc0_s[30] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 111 p16 pj[8] pcr[152] af0 af1 af2 af3 ? gpio[152] ? ? ? adc0_s[31] siul ? ? ? adc_0 i/o ? ? ? i s tristate ? 110 p15 pj[9] pcr[153] af0 af1 af2 af3 ? gpio[153] ? ? ? adc1_s[8] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 68 p5 pj[10] pcr[154] af0 af1 af2 af3 ? gpio[154] ? ? ? adc1_s[9] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 67 t5 pj[11] pcr[155] af0 af1 af2 af3 ? gpio[155] ? ? ? adc1_s[10] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 60 r3 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 34 pj[12] pcr[156] af0 af1 af2 af3 ? gpio[156] ? ? ? adc1_s[11] siul ? ? ? adc_1 i/o ? ? ? i stristate ? 59 t1 pj[13] pcr[157] af0 af1 af2 af3 ? ? ? ? gpio[157] ? cs1_7 ? can4rx adc1_s[12] can1rx wkpu[31] siul ? dspi_7 ? flexcan_4 adc_1 flexcan_1 wkpu i/o ? o ? i i i i stristate ? 65 n5 pj[14] pcr[158] af0 af1 af2 af3 gpio[158] can1tx can4tx cs2_7 siul flexcan_1 flexcan_4 dspi_7 i/o o o o m/s tristate ? 64 t4 pj[15] pcr[159] af0 af1 af2 af3 ? gpio[159] ? cs1_6 ? can1rx siul ? dspi_6 ? flexcan_1 i/o ? o ? i m/s tristate ? 63 r4 pk[0] pcr[160] af0 af1 af2 af3 gpio[160] can1tx cs2_6 ? siul flexcan_1 dspi_6 ? i/o o o ? m/s tristate ? 62 t3 pk[1] pcr[161] af0 af1 af2 af3 ? gpio[161] cs3_6 ? ? can4rx siul dspi_6 ? ? flexcan_4 i/o o ? ? i m/s tristate ? 41 h4 pk[2] pcr[162] af0 af1 af2 af3 gpio[162] can4tx ? ? siul flexcan_4 ? ? i/o o ? ? m/s tristate ? 42 l4 pk[3] pcr[163] af0 af1 af2 af3 ? ? gpio[163] e1uc[0] ? ? can5rx lin8rx siul emios_1 ? ? flexcan_5 linflexd_8 i/o i/o ? ? i i m/s tristate ? 43 n1 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 35 pk[4] pcr[164] af0 af1 af2 af3 gpio[164] lin8tx can5tx e1uc[1] siul linflexd_8 flexcan_5 emios_1 i/o o o i/o m/s tristate ? 44 m3 pk[5] pcr[165] af0 af1 af2 af3 ? ? gpio[165] ? ? ? can2rx lin2rx siul ? ? ? flexcan_2 linflexd_2 i/o ? ? ? i i m/s tristate ? 45 m5 pk[6] pcr[166] af0 af1 af2 af3 gpio[166] can2tx lin2tx ? siul flexcan_2 linflexd_2 ? i/o o o ? m/s tristate ? 46 m6 pk[7] pcr[167] af0 af1 af2 af3 ? ? gpio[167] ? ? ? can3rx lin3rx siul ? ? ? flexcan_3 linflexd_3 i/o ? ? ? i i m/s tristate ? 47 m7 pk[8] pcr[168] af0 af1 af2 af3 gpio[168] can3tx lin3tx ? siul flexcan_3 linflexd_3 ? i/o o o ? m/s tristate ? 48 m8 pk[9] pcr[169] af0 af1 af2 af3 ? gpio[169] ? ? ? sin_4 siul ? ? ? dspi_4 i/o ? ? ? i m/s tristate ? 197 e8 pk[10] pcr[170] af0 af1 af2 af3 gpio[170] sout_4 ? ? siul dspi_4 ? ? i/o o ? ? m/s tristate ? 198 e7 pk[11] pcr[171] af0 af1 af2 af3 gpio[171] sck_4 ? ? siul dspi_4 ? ? i/o i/o ? ? m/s tristate ? 199 f8 pk[12] pcr[172] af0 af1 af2 af3 gpio[172] cs0_4 ? ? siul dspi_4 ? ? i/o i/o ? ? m/s tristate ? 200 g12 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 36 pk[13] pcr[173] af0 af1 af2 af3 ? gpio[173] cs3_6 cs2_7 sck_1 can3rx siul dspi_6 dspi_7 dspi_1 flexcan_3 i/o o o i/o i m/s tristate ? 201 h12 pk[14] pcr[174] af0 af1 af2 af3 gpio[174] can3tx cs3_7 cs0_1 siul flexcan_3 dspi_7 dspi_1 i/o o o i/o m/s tristate ? 202 j12 pk[15] pcr[175] af0 af1 af2 af3 ? ? gpio[175] ? ? ? sin_1 sin_7 siul ? ? ? dspi_1 dspi_7 i/o ? ? ? i i m/s tristate ? 203 d5 pl[0] pcr[176] af0 af1 af2 af3 gpio[176] sout_1 sout_7 ? siul dspi_1 dspi_7 ? i/o o o ? m/s tristate ? 204 c4 pl[1] pcr[177] af0 af1 af2 af3 gpio[177] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? f7 pl[2] pcr[178] 7 af0 af1 af2 af3 gpio[178] ? mdo0 8 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f5 pl[3] pcr[179] af0 af1 af2 af3 gpio[179] ? mdo1 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? g5 pl[4] pcr[180] af0 af1 af2 af3 gpio[180] ? mdo2 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? h5 pl[5] pcr[181] af0 af1 af2 af3 gpio[181] ? mdo3 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? j5 pl[6] pcr[182] af0 af1 af2 af3 gpio[182] ? mdo4 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? k5 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 37 pl[7] pcr[183] af0 af1 af2 af3 gpio[183] ? mdo5 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? l5 pl[8] pcr[184] af0 af1 af2 af3 ? gpio[184] ? ? ? evti siul ? ? ? nexus i/o ? ? ? i s pull-up ? ? m9 pl[9] pcr[185] af0 af1 af2 af3 gpio[185] ? mseo0 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? m10 pl[10] pcr[186] af0 af1 af2 af3 gpio[186] ? mcko ? siul ? nexus ? i/o ? o ? f/s tristate ? ? m11 pl[11] pcr[187] af0 af1 af2 af3 gpio[187] ? mseo1 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? m12 pl[12] pcr[188] af0 af1 af2 af3 gpio[188] ? evto ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f11 pl[13] pcr[189] af0 af1 af2 af3 gpio[189] ? mdo6 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f10 pl[14] pcr[190] af0 af1 af2 af3 gpio[190] ? mdo7 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e12 pl[15] pcr[191] af0 af1 af2 af3 gpio[191] ? mdo8 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e11 pm[0] pcr[192] af0 af1 af2 af3 gpio[192] ? mdo9 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e10 table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 38 pm[1] pcr[193] af0 af1 af2 af3 gpio[193] ? mdo10 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? e9 pm[2] pcr[194] af0 af1 af2 af3 gpio[194] ? mdo11 ? siul ? nexus ? i/o ? o ? m/s tristate ? ? f12 pm[3] pcr[195] af0 af1 af2 af3 gpio[195] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? k12 pm[4] pcr[196] af0 af1 af2 af3 gpio[196] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? l12 pm[5] pcr[197] af0 af1 af2 af3 gpio[197] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? f9 pm[6] pcr[198] af0 af1 af2 af3 gpio[198] ? ? ? siul ? ? ? i/o ? ? ? m/s tristate ? ? f6 1 alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 000 ? af0; pcr.pa = 001 ? af1; pcr.pa = 010 ? af2; pcr.pa = 011 ? af3; pcr.pa = 100 ? alt4. this is intended to select the output functions; to use one of the input functions, t he pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 multiple inputs are routed to all respective modules internally. the input of some modules must be configured by setting the values of the psmio.padselx bitfields inside the siul module. 3 nmi[0] and nmi[1] have a higher priority than alternat e functions. when nmi is selected, the pcr.pa field is ignored. 4 sxosc?s osc32k_xtal and osc32k_extal pins are shared with gpio functionality. when used as crystal pins, other functionality of the pin cannot be used and it should be ensured that application never programs obe and pue bit of the corresponding pcr to "1". 5 if you want to use osc32k functionality through pb[8] and pb[9], you must ensure that pb[10] is static in nature as pb[10] can induce coupling on pb[ 9] and disturb oscillator frequency. 6 out of reset all the functional pins except pc[0:1] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). it is up to the user to configur e these pins as gpio when needed. table 4. functional port pin descriptions (continued) port pin pcr alternate function 1 function peripheral i/o direction 2 pad type reset config. pin number 176 lqfp 208 lqfp 256 mapbga
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 39 4 electrical characteristics this section contains electrical char acteristics of the device as well as temperature and power considerations. this product contains devices to protect the inputs against damage due to high static voltages. however, it is advisable to tak e precautions to avoid application of any voltage higher than the specified maximum rated voltages. to enhance reliability, unused inputs can be dr iven to an appropriat e logic voltage level (v dd or v ss_hv ). this could be done by the internal pull-up and pull-down, which is prov ided by the product for most general purpose pins. the parameters listed in the following tables represent th e characteristics of the device and its demands on the system. in the tables where the device lo gic provides signals with their respective timing characteristics, the symbol ?cc? for control ler characteristics is included in the symbol column. in the tables where the external system mu st provide signals with their respective timing characteristics to the device, the sy mbol ?sr? for system requirement is included in the symbol column. 4.1 parameter classification the electrical parameters shown in this supplement are guaranteed by various methods. to give the customer a better understanding, the classifications listed in table 5 are used and the parameters are ta gged accordingly in the tables where appropriate. note the classification is shown in the column labeled ?c? in the parameter tables where appropriate. 4.2 nvusro register portions of the device configuration, such as high voltage supply is controlled via bit values in the non-volatile user options register (nvusro). for a detailed description of the nvusro register, see mpc5646c reference manual. 7 when mbist is enabled to run ( stcu enable = 1), the applic ation must not drive or tie pad[178) (mdo[0]) to 0 v before the device exits reset (external reset is removed) as the pad is internally driven to 1 to indicate mbist operation. when mbist is not enabled (stcu enable = 0), th ere are no restriction as the device does not internally drive the pad. 8 these pins can be configured as nexus pins during rese t by the debugger writing to the nexus development interface "port control register" rather than the siul. specifically, the debugger can enable the mdo[7:0], mseo[1:0], and mcko ports by programming ndi (pcr[ mcko_en] or pcr[pstat_en]). mdo[8:11] ports can be enabled by programming ndi ((pcr[mc ko_en] and pcr[fpm]) or pcr[pstat_en]). table 5. paramete r classifications classification ta g tag description p those parameters are guaranteed during production testing on each individual device. c those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. t those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. all values shown in the typical column are within this category. d those parameters are derived mainly from simulations.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 40 4.2.1 nvusro [pad3v5v(0)] field description table 6 shows how nvusro [pad3v5v(0)] contro ls the device configuration for v dd_hv_a domain. the dc electrical characteristics are de pendent on the pad3v5v(0,1) bit value. 4.2.2 nvusro [pad3v5v(1)] field description table 7 shows how nvusro [pad3v5v(1)] controls the devi ce configuration the device configuration for v dd_hv_b domain. the dc electrical characteristics are de pendent on the pad3v5v(0,1) bit value. 4.3 absolute maximum ratings table 6. pad3v5v(0) field description value 1 1 '1' is delivery value. it is part of shadow flash memory, thus programmable by customer. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 7. pad3v5v(1) field description value 1 1 '1' is delivery value. it is part of shadow flash memory, thus programmable by customer. description 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v table 8. absolute maximum ratings symbol parameter conditions value unit min max v ss_hv sr digital ground on vss_hv pins ?00v v dd_hv_a sr voltage on vdd_hv_a pins with respect to ground (v ss_hv ) ??0.36.0v v dd_hv_b 1 sr voltage on vdd_hv_b pins with respect to common ground (v ss_hv ) ??0.36.0v v ss_lv sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss_hv ) ?v ss_hv ? 0.1 v ss_hv ? 0.1 v v rc_ctrl 2 base control voltage for external bcp68 npn device relative to v dd_lv 0v dd_lv +1 v
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 41 note stresses exceeding the recommended absolute maximum ratings ma y cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi cated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device re liability. during overload conditions (v in > v dd_hv_a/hv_b or v in mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 42 4.4 recommended operating conditions table 9. recommended operating conditions (3.3 v) symbol parameter conditions value unit min max v ss_hv sr digital ground on vss_hv pins ?00v v dd_hv_a 1 1 100 nf emi capacitance and 10 f bulk capacitance need to be provided between each v dd /v ss_hv pair. sr voltage on v dd_hv_a pins with respect to ground (v ss_hv ) ?3.03.6v v dd_hv_b 1 sr voltage on v dd_hv_b pins with respect to ground (v ss_hv ) ?3.03.6v v ss_lv 2 sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss_hv ) ?v ss_hv ? 0.1 v ss_hv +0.1 v v rc_ctrl 3 base control voltage for external bcp68 npn device relative to v dd_lv 0v dd_lv +1 v v ss_adc sr voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss_hv ) ?v ss_hv ? 0.1 v ss_hv +0.1 v v dd_hv_adc0 4 sr voltage on vdd_hv_adc0 with respect to ground (v ss_hv ) ?3.0 5 3.6 v relative to v dd_hv_a 6 v dd_hv_a ? 0.1 v dd_hv_a + 0.1 v dd_hv_adc1 7 sr voltage on vdd_hv_adc1 with respect to ground (v ss_hv ) ?3.03.6v relative to v dd_hv_a 6 v dd_hv_a ? 0.1 v dd_hv_a +0.1 v in sr voltage on any gpio pin with respect to ground (v ss_hv ) ?v ss_hv ? 0.1 ? v relative to v dd_hv_a/hv_b ?v dd_hv_a/hv_b +0.1 i injpad sr injected input current on any pin during overload condition ? ? 55ma i injsum sr absolute sum of all injected input currents during overload condition ? ? 50 50 tv dd sr v dd_hv_a slope to ensure correct power up 8 ??0.5v/s ? 0.5 ? v/min t a sr ambient temperature under bias f cpu up to 120 mhz ? 2% ?40 125 c t j sr junction temperature under bias ? ? 40 150
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 43 2 100 nf emi capacitance and 10 f bulk capacitance ne ed to be provided between each of the four v dd_lv /v ss_lv supply pairs. for details refer to the power manag ement chapter of the mpc5646c reference manual. 3 this voltage is internally generated by the de vice and no external voltage should be supplied. 4 100 nf capacitance needs to be provided between v dd_adc /v ss_adc pair. 5 full electrical specification cannot be guaranteed when vo ltage drops below 3.0 v. in particular, adc electrical characteristics and i/os dc electrical specification may not be guaranteed. when voltage drops below v lv d h v l , device is reset. 6 both the relative and the fixed conditions must be met. for instance: if v dd_hv_a is 5.9 v, v dd_hv_adc0 maximum value is 6.0 v then, despite the relative condition, the max value is v dd_hv_a +0.3=6.2v. 7 pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence v dd_hv_adc1 should be within 100 mv of v dd_hv_b when these channels are used for adc_1. 8 guaranteed by the device validation. table 10. recommended operating conditions (5.0 v) symbol parameter conditions value unit min max v ss_hv sr digital ground on vss_hv pins ? 0 0 v v dd_hv_a 1 sr voltage on vdd_hv_a pins with respect to ground (v ss_hv ) ?4.55.5v voltage drop 2 3.0 5.5 v dd_hv_b sr generic gpio functionality ? 3.0 5.5 v ethernet/3.3 v functionality (see the notes in all figures in section 3, ?package pinouts and signal descriptions ? for the list of channels operating in v dd_hv_b domain) ?3.03.6v v ss_lv 3 sr voltage on vss_lv (low voltage digital supply) pins with respect to ground (v ss_hv ) ?v ss_hv ?0.1 v ss_hv +0.1 v v rc_ctrl 4 base control voltage for external bcp68 npn device relative to v dd_lv 0v dd_lv +1 v v ss_adc sr voltage on vss_hv_adc0, vss_hv_adc1 (adc reference) pin with respect to ground (v ss_hv ) ?v ss_hv ?0.1 v ss_hv +0.1 v v dd_hv_adc0 5 sr voltage on vdd_hv_adc0 with respect to ground (v ss_hv ) ?4.55.5v voltage drop (2) 3.0 5.5 relative to v dd_hv_a 6 v dd_hv_a ?0.1 v dd_hv_a +0.1 v dd_hv_adc1 7 sr voltage on vdd_hv_adc1 with respect to ground (v ss_hv ) ?4.55.5v voltage drop (2) 3.0 5.5 relative to v dd_hv_a 6 v dd_hv_a ? 0.1 v dd_hv_a +0.1
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 44 note sram retention guaranteed to lvd levels. v in sr voltage on any gpio pin with respect to ground (v ss_hv ) ?v ss_hv ?0.1 ? v relative to v dd_hv_a/hv_b ?v dd_hv_a/hv_b +0.1 i injpad sr injected input current on any pin during overload condition ??5 5ma i injsum sr absolute sum of all injected input currents during overload condition ? ?50 50 tv dd sr v dd_hv_a slope to ensure correct power up 8 ??0.5v/s ? 0.5 ? v/min t a c-grade part sr ambient temperature under bias ? ? 40 85 c t j c-grade part sr junction temperature under bias ? ? 40 110 t a v-grade part sr ambient temperature under bias ? ? 40 105 t j v-grade part sr junction temperature under bias ? ? 40 130 t a m-grade part sr ambient temperature under bias ? ? 40 125 t j m-grade part sr junction temperature under bias ? ? 40 150 1 100 nf emi capacitance and 10 f bulk capacitance needs to be provided between each v dd_hv_a/hv_b /v ss_hv pair. 2 full device operation is guaranteed by design from 3.0 v?5. 5 v. osc electrical characteristics (startup time, idd, negative resistance, esr and duty cycle) will not be guarant eed to stay within the stated limits when operating below 4.5 v and above 3.6 v. however, osc functionality is guaranteed within the entire range (3.0 v?5.5 v). 3 100 nf emi capacitance and 40 f bulk capacitance needs to be provided between each v dd_lv /v ss_lv supply pair. 4 this voltage is internally generated by the device and no external voltage should be supplied. 5 100 nf capacitance needs to be provided between v dd_hv_(adc0/adc1) /v ss_hv_(adc0/adc1) pair. 6 both the relative and the fixed conditions must be met. for instance: if v dd_hv_a is 5.9 v, v dd_hv_adc0 maximum value is 6.0 v then, despite the relative condition, the max value is v dd_hv_a +0.3=6.2v. 7 pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence vdd_hv_adc1 should be within 100 mv of v dd_hv_b when these channels are used for adc_1. 8 guaranteed by device validation. table 10. recommended operating conditions (5.0 v) (continued) symbol parameter conditions value unit min max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 45 4.5 thermal characteristics 4.5.1 package thermal characteristics 4.5.2 power considerations the average chip-junction temperature, t j , in degrees celsius, may be calculated using equation 1 : t j = t a + (p d ? r ? ja ) eqn. 1 where: t a is the ambient temperature in c. r ? ja is the package junction-to-ambie nt thermal resistance, in c/w. p d is the sum of p int and p i/o (p d =p int + p i/o ). p int is the product of i dd and v dd , expressed in watts. this is the chip internal power. p i/o represents the power dissipation on input and output pins; user determined. table 11. lqfp thermal characteristics 1 1 thermal characteristics are targets based on simulation that are subject to change per device characterization. symbol c parameter conditions 2 2 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c. pin count value 3 3 all values need to be confirmed during device validation. unit min typ max r ? ja cc d thermal resistance, junction-to-ambient natural convection 4 4 junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, powe r dissipation of other component s on the board, and board thermal resistance. single-layer board?1s 176 ? ? 38 5 5 junction-to-ambient thermal resistance determined per jedec jesd51-3 and jesd51-6. c/w 208 ? ? 41 6 6 junction-to-ambient thermal resistance determined per jedec jesd51-2 and jesd51-6 c/w r ? ja cc d thermal resistance, junction-to-ambient natural convection 7 four-layer board?2s2p 7 7 junction-to-board thermal resistance determined per jedec jesd51-8. 176 ? ? 31 c/w 208 ? ? 34 c/w table 12. 256 mapbga thermal characteristics 1 1 thermal characteristics are targets based on simulation t hat are subject to change per device characterization. symbol c parameter conditions value unit r ? ja cc ? thermal resistance, junction-to-ambient natural convection single-layer board?1s 43 2 2 junction-to-ambient thermal resistance determined per jedec jesd51-2 with the single layer board horizontal. board meets jesd51-9 specification. c/w four-layer board?2s2p 26 3 3 junction-to-ambient thermal resistance determined per jedec jesd51-6 with the board horizontal.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 46 most of the time for the applications, p i/o < p int and may be neglected. on the other hand, p i/o may be significant, if the device is configured to continuously drive external modules and/or memories. an approximate relationship between p d and t j (if p i/o is neglected) is given by: p d = k / (t j + 273 c) eqn. 2 therefore, solving equations 1 and 2 : k = p d ? (t a + 273 c) + r ? ja ? p d 2 eqn. 3 where: k is a constant for the particular part, which may be determined from equation 3 by measuring p d (at equilibrium) for a known t a. using this value of k, the values of p d and t j may be obtained by solving equations 1 and 2 iteratively for any value of t a . 4.6 i/o pad electrical characteristics 4.6.1 i/o pad types the device provides four main i/o pad types depe nding on the associated alternate functions: ? slow pads?these pads are the most common pads, providing a good compromise between transition time and low electromagnetic emission. ? medium pads?these pads provide transition fast enough for the serial communicati on channels with controlled current to reduce elect romagnetic emission. ? fast pads?these pads provide maximum speed. these are used for improved nexus debugging capability. ? input only pads?these pads are associated to adc ch annels and 32 khz low power external crystal oscillator providing low input leakage. ? low power pads?these pads are active in standby mode for wakeup source. also, medium/slow and fast/medium pads ar e available in design which can be configured to behave like a slow/medium and medium/fast pads depending upon the slew-rate control. medium and fast pads can use slow configuration to reduce elect romagnetic emission, at the cost of reducing ac performance. 4.6.2 i/o input dc characteristics table 13 provides input dc electrical ch aracteristics as described in figure 5 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 47 figure 5. i/o input dc electrical characteristics definition 4.6.3 i/o output dc characteristics the following tables provide dc char acteristics for bidirectional pads: table 13. i/o input dc electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . all values need to be confirmed during device validation. unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il sr p input low level cmos (schmitt trigger) ? ? 0.3 ? 0.35v dd v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ?? i lkg cc p digital input leakage no injection on adjacent pin t a = ? 40 c ? 2 ? na pt a = 25 c ? 2 ? dt a = 105 c ? 12 500 pt a = 125 c ? 70 1000 w fi sr p width of input pulse rejected by analog filter 3 3 analog filters are available on all wakeup lines. ???40 4 ns w nfi sr p width of input pulse accepted by analog filter (3) ? 1000 4 4 the width of input pulse in between 40 ns to 1000 ns is indeterminate. it may pass the noise or may not depending on silicon sample to sample variation. ??ns v il v in v ih pdix = ?1 v dd v hys (gpdi register of siul) pdix = ?0?
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 48 ? table 14 provides weak pull figures. both pull- up and pull-down resistances are supported. ? table 15 provides output driver char acteristics for i/o pads wh en in slow configuration. ? table 16 provides output driver char acteristics for i/o pads when in medium configuration. ? table 17 provides output driver char acteristics for i/o pads wh en in fast configuration. table 14. i/o pull-up/pull-down dc electrical characteristics symbol c parameter conditions 1,2 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . value unit min typ max |i wpu | cc p weak pull-up current absolute value v in = v il , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a cpad3v5v = 1 3 3 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 10 ? 250 pv in = v il , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 |i wpd | cc p weak pull-down current absolute value v in = v ih , v dd = 5.0 v 10% pad3v5v = 0 10 ? 150 a c pad3v5v = 1 10 ? 250 pv in = v ih , v dd = 3.3 v 10% pad3v5v = 1 10 ? 150 table 15. slow configuration output buffer electrical characteristics symbol c parameter conditions 1,2 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . value unit min typ max v oh cc p output high level slow configuration push pull i oh = ? 3ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ??v ci oh = ? 3ma, v dd = 5.0 v 10%, pad3v5v = 1 3 3 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are c onfigured in input or in high impedance state. 0.8v dd ?? pi oh = ? 1.5 ma, v dd = 3.3 v 10%, pad3v5v = 1 v dd ? 0.8 ? ? v ol cc p output low level slow configuration push pull i ol =3ma, v dd = 5.0 v 10%, pad3v5v = 0 ? ? 0.1v dd v ci ol = 3 ma, v dd = 5.0 v 10%, pad3v5v = 1 (3) ? ? 0.1v dd pi ol = 1.5 ma, v dd = 3.3 v 10%, pad3v5v = 1 ??0.5
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 49 table 16. medium configuration output buffer electrical characteristics symbol c parameter conditions 1 , 2 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . value unit min typ max v oh cc c output high level medium configuration push pull i oh = ? 3ma, v dd = 5.0 v 10%, pa d 3 v 5 v = 0 0.8v dd ?? v ci oh = ? 1.5 ma, v dd = 5.0 v 10%, pa d 3 v 5 v = 1 3 3 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. 0.8v dd ?? ci oh = ? 2ma, v dd = 3.3 v 10%, pa d 3 v 5 v = 1 v dd ? 0.8 ? ? v ol cc c output low level medium configuration push pull i ol = 3 ma, v dd = 5.0 v 10%, pa d 3 v 5 v = 0 ? ? 0.2v dd v ci ol = 1.5 ma, v dd = 5.0 v 10%, pa d 3 v 5 v = 1 (3) ? ? 0.1v dd ci ol = 2 ma, v dd = 3.3 v 10%, pa d 3 v 5 v = 1 ??0.5 table 17. fast configuration output buffer electrical characteristics symbol c parameter conditions 1,2 value unit min typ max v oh cc p output high level fast configuration push pull i oh = ? 14 ma, v dd = 5.0 v 10%, pad3v5v = 0 0.8v dd ??v ci oh = ? 7ma, v dd = 5.0 v 10%, pad3v5v = 1 3 0.8v dd ?? ci oh = ? 11 ma, v dd = 3.3 v 10%, pad3v5v = 1 v dd ? 0.8 ? ?
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 50 4.6.4 output pin transition times v ol cc p output low level fast configuration push pull i ol = 14 ma, v dd = 5.0 v 10%, pad3v5v = 0 ??0.1v dd v ci ol = 7 ma, v dd = 5.0 v 10%, pad3v5v = 1 (3) ??0.1v dd ci ol = 11 ma, v dd = 3.3 v 10%, pad3v5v = 1 ??0.5 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3 the configuration pad3v5 = 1 when v dd = 5 v is only a transient configuration during power-up. all pads but reset and nexus outputs (mdox, evto, mcko) are co nfigured in input or in high impedance state. table 18. output pin transition times symbol c parameter conditions 1,2 value 3 unit min typ max t tr cc d output transition time output pin 4 slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ? ? 50 ns tc l = 50 pf ? ? 100 dc l = 100 pf ? ? 125 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ??40 tc l = 50 pf ? ? 50 dc l = 100 pf ? ? 75 t tr cc d output transition time output pin (4) medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 siul.pcrx.src = 1 ? ? 10 ns tc l = 50 pf ? ? 20 dc l = 100 pf ? ? 40 dc l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 siul.pcrx.src = 1 ??12 tc l = 50 pf ? ? 25 dc l = 100 pf ? ? 40 table 17. fast configuration output buffer electrical characteristics (continued) symbol c parameter conditions 1,2 value unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 51 4.6.5 i/o pad current specification the i/o pads are distributed across the i/o supply segment. each i/ o supply is associated to a v dd /v ss_hv supply pair as described in table 19 . table 20 provides i/o consumption figures. in order to ensure device reliability, the average current of the i/o on a si ngle segment should remain below the i av g s e g maximum value. in order to ensure device functionality, the sum of the dynamic and static current of the i/o on a single segment should remain below the i dynseg maximum value. t tr cc d output transition time output pin (4) fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ?? 4ns c l = 50 pf ? ? 6 c l = 100 pf ? ? 12 c l = 25 pf v dd = 3.3 v 10%, pad3v5v = 1 ?? 4 c l = 50 pf ? ? 7 c l = 100 pf ? ? 12 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . 3 all values need to be confirmed during device validation. 4 c l includes device and package capacitances (c pkg < 5 pf). table 19. i/o supplies package i/o supplies 256 mapbga equivalent to 208-pin lqfp segment pad distribution + g6, g11, h11, j11 208 lqfp pin6 (v dd_hv_a ) pin7 (v ss_hv ) pin27 (v dd_hv_a ) pin28 (v ss_hv ) pin73 (v ss_hv ) pin75 (v dd_hv_a ) pin101 (v dd_hv_a ) pin102 (v ss_hv ) pin132 (v ss_hv ) pin133 (v dd_hv_a ) pin147 (v ss_hv ) pin148 (v dd_hv_b ) pin174 (v ss_hv ) pin175 (v dd_hv_a ) ? 176 lqfp pin6 (v dd_hv_a ) pin7 (v ss_hv ) pin27 (v dd_hv_a ) pin28 (v ss_hv ) pin57 (v ss_hv ) pin59 (v dd_hv_a ) pin85 (v dd_hv_a ) pin86 (v ss_hv ) pin123 (v ss_hv ) pin124 (v dd_hv_b ) pin150 (v ss_hv ) pin151 (v dd_hv_a ) ?? table 18. output pin transition times (continued) symbol c parameter conditions 1,2 value 3 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 52 table 20. i/o consumption symbol c parameter conditions 1,2 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . value 3 3 all values need to be confirmed during device validation. unit min typ max i swtslw ,4 4 stated maximum values represent peak consumption that lasts only a few ns during i/o transition. cc d peak i/o current for slow configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??19.9 ma v dd = 3.3 v 10%, pad3v5v = 1 ??15.5 i swtmed (4) cc d peak i/o current for medium configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ??28.8 ma v dd = 3.3 v 10%, pad3v5v = 1 ??16.3 i swtfst (4) cc d peak i/o current for fast configuration c l = 25 pf v dd = 5.0 v 10%, pad3v5v = 0 ? ? 113.5 ma v dd = 3.3 v 10%, pad3v5v = 1 ??52.1 i rmsslw cc d root mean square i/o current for slow configuration c l = 25 pf, 2 mhz v dd = 5.0 v 10%, pad3v5v = 0 ? ? 2.22 ma c l = 25 pf, 4 mhz ? ? 3.13 c l = 100 pf, 2 mhz ? ? 6.54 c l = 25 pf, 2 mhz v dd = 3.3 v 10%, pad3v5v = 1 ? ? 1.51 c l = 25 pf, 4 mhz ? ? 2.14 c l = 100 pf, 2 mhz ? ? 4.33 i rmsmed cc d root mean square i/o current for medium configuration c l = 25 pf, 13 mhz v dd = 5.0 v 10%, pad3v5v = 0 ??6.5ma c l = 25 pf, 40 mhz ? ? 13.32 c l = 100 pf, 13 mhz ? ? 18.26 c l = 25 pf, 13 mhz v dd = 3.3 v 10%, pad3v5v = 1 ? ? 4.91 c l = 25 pf, 40 mhz ? ? 8.47 c l = 100 pf, 13 mhz ? ? 10.94 i rmsfst cc d root mean square i/o current for fast configuration c l = 25 pf, 40 mhz v dd = 5.0 v 10%, pad3v5v = 0 ? ? 21.05 ma c l = 25 pf, 64 mhz ? ? 33 c l = 100 pf, 40 mhz ? ? 55.77 c l = 25 pf, 40 mhz v dd = 3.3 v 10%, pad3v5v = 1 ??14 c l = 25 pf, 64 mhz ? ? 20 c l = 100 pf, 40 mhz ? ? 34.89 i avgseg sr d sum of all the static i/o current within a supply segment v dd = 5.0 v 10%, pad3v5v = 0 ? ? 70 ma v dd = 3.3 v 10%, pad3v5v = 1 ? ? 65 4
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 53 4.7 reset electrical characteristics the device implements a dedi cated bidirectional reset pin. figure 6. start-up reset requirements figure 7. noise filtering on reset signal table 21. reset electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max v ih sr p input high level cmos (schmitt trigger) ?0.65v dd ?v dd +0.4 v v il v dd_hv_a device reset forced by reset v ddmin reset v ih device start-up phase v reset v il v ih v dd filtered by hysteresis filtered by lowpass filter w frst w nfrst hw_rst ?1? ?0? filtered by lowpass filter w frst unknown reset state device under hardware reset
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 54 v il sr p input low level cmos (schmitt trigger) ? ? 0.3 ? 0.35v dd v v hys cc c input hysteresis cmos (schmitt trigger) ?0.1v dd ??v v ol cc p output low level push pull, i ol = 2 ma, v dd = 5.0 v 10%, pad3v5v = 0 (recommended) ? ? 0.1v dd v push pull, i ol = 1 ma, v dd = 5.0 v 10%, pad3v5v = 1 3 ? ? 0.1v dd push pull, i ol = 1 ma, v dd = 3.3 v 10%, pad3v5v = 1 (recommended) ??0.5 t tr cc d output transition time output pin 4 medium configuration c l = 25 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 10ns c l = 50 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 20 c l = 100 pf, v dd = 5.0 v 10%, pad3v5v = 0 ?? 40 c l = 25 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 12 c l = 50 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 25 c l = 100 pf, v dd = 3.3 v 10%, pad3v5v = 1 ?? 40 w frst sr p reset input filtered pulse ? ? ? 40 ns w nfrst sr p reset input not filtered pulse ? 1000 ? ? ns |i wpu | cc p weak pull-up current absolute value v dd = 3.3 v 10%, pad3v5v = 1 10 ? 150 a v dd = 5.0 v 10%, pad3v5v = 0 10 ? 150 v dd = 5.0 v 10%, pad3v5v = 1 5 10 ? 250 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 v dd as mentioned in the table is v dd_hv_a /v dd_hv_b . all values need to be confirmed during device validation. 3 this is a transient configuration during power-up, up to the end of reset phase2 (refe r to the rgm module section of the device reference manual). 4 c l includes device and package capacitance (c pkg <5pf). 5 the configuration pad3v5 = 1 when v dd = 5 v is only transient configuration during power-up. all pads but reset and nexus output (mdox, evto, mcko) are configured in input or in high impedance state. table 21. reset electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 55 4.8 power management electrical characteristics 4.8.1 voltage regulator electrical characteristics the device implements an internal voltage regulator to generate the low voltage core supply v dd_lv from the high voltage supply v dd_hv_a . the following supplies are involved: ? hv: high voltage external power supply for voltage regulator module. this must be provided externally through v dd_hv_a power pin. ? lv: low voltage internal power supply for core, fmpll and flash digital logic. this is generated by the on-chip vreg with an external ballast (bcp68 npn device). it is further split into four main domains to ensure noise isolation between critical lv modules within the device: ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ? lv_cfla0/cfla1: low voltage supply for the two code flash modules. it is shorted with lv_cor through double bonding. ? lv_dfla: low voltage supply for data flash module. it is shorted with lv_cor through double bonding. ? lv_pll: low voltage supply for fmpll. it is shorted to lv_cor through double bonding. figure 8. voltage regulator capacitance connection the internal voltage regulator re quires external bulk capacitance (c regn ) to be connected to the device to provide a stable low voltage digital supply to the device. also required for stability is the c dec2 capacitor at ballast collector. this is needed to minimize sharp injection current when ballast is turning on. apart from the bulk capacitance, user should connect 32 kb 56 kb split split ctrl ctrl split ctrl pd0 (always on domain) pd1 switchable domain hpreg lpreg hpvdd lpvdd vdd_lv vss_lv off chip bcp68 40 ? f hpvdd lpvdd sw1 (<0.1 ? ) 8kb pd0 logic vdd_bv vdd_hv_a vss_hv 100 nf (fmpll, flash) vdd_lv vdd_lv vdd_lv vss_lv vss_lv vss_lv 100 nf 100 nf 100 nf vrc_ctrl (c regn ) chip boundary 10 ? f (c dec2 ) (4 ? 10 ? f) npn driver
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 56 emi/decoupling cap (c regp ) at each v dd_lv /v ss_lv pin pair. 4.8.1.1 recommendations ? the external npn driver must be bcp68 type. ?v dd_lv should be implemented as a power plane fr om the emitter of the ballast transistor. ?10 ? f capacitors should be connected to the 4 pins closest to the outside of the package and should be evenly distributed around the package. for bga packages, the balls should be used are d8, h14, r9, j3?one cap on each side of package. ? there should be a track direct from the cap acitor to this pin (pin also connects to v dd_lv plane). the tracks esr should be less than 100 m ? . ? the remaining v dd_lv pins (exact number will vary with package) should be decoupled with 0.1 ? f caps, connected to the pin as per 10 ? f. (see section 4.4, ?recommende d operating conditions ?). 4.8.2 v dd_bv options ? option 1: v dd_bv shared with v dd_hv_a v dd_bv must be star routed from v dd_hv_a from the common source. this is to eliminate ballast noise injection on the mcu. ? option 2: v dd_bv independent of the mcu supply v dd_bv > 2.6 v for correct functionality. the device is not monitoring this supply hence the external component must meet the 2.6 v criteria through external monitoring if required. table 22. voltage regulator electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max c regn sr ? external ballast st ability capacitance ? 40 ? 60 ? f r reg sr ? stability capacitor equivalent serial resistance ???0.2 ? c regp sr ? decoupling capacitance (close to the pin) v dd_hv_a/hv_b /v ss_hv pair 100 ? nf v dd_lv /v ss_lv pair 100 ? nf c dec2 sr ? stability capacitance regulator supply (close to the ballast collector) v dd_hv_a /v ss_hv 10 ? 40 ? f v mreg cc p main regulator output voltage before trimming ? 1.32 ? v after trimming ? 1.28 ? i mreg sr ? main regulator current provided to v dd_lv domain ??? 350 ma i mregint cc d main regulator module current consumption i mreg = 200 ma ? ? 2 ma i mreg = 0 ma ? ? 1 v lpreg cc p low power regulator output voltage after trimming ? 1.23 ? v i lpreg sr ? low power regulator current provided to v dd_lv domain ? ?? 50 ma
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 57 4.8.3 voltage monitor electrical characteristics the device implements a power-on reset module to ensure correct power-up initialization, as well as four low voltage detectors to monitor the v dd_hv_a and the v dd_lv voltage while device is supplied: ? por monitors v dd_hv_a during the power-up phase to ensure devi ce is maintained in a safe reset state ? lvdhv3 monitors v dd_hv_a to ensure device is reset below minimum functional supply ? lvdhv5 monitors v dd_hv_a when application uses de vice in the 5.0 v10% range ? lvdlvcor monitors power domain no. 1 (pd1) ? lvdlvbkp monitors power domain no. 0 (pd0). vdd_lv is same as pd0 supply. note when enabled, pd2 (ram retention) is monitored through lvd_digbkp. i lpregint cc d low power regulator module current consumption i lpreg = 15 ma; t a = 55 c ?? 600 ? a ? i lpreg = 0 ma; t a = 55 c ? 20 ? i vregref cc d main lvds and reference current consumption (low power and main regulator switched off) t a = 55 c ? 2 ? ? a i vredlvd12 cc d main lvd current consumption (switch-off during standby) t a = 55 c ? 1 ? ? a i dd_hv_a cc d in-rush current on v dd_hv_a 3 during power-up ?? ? 600 4 ma 1 v dd_hv_a = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 assumption is v dd_hv_a is now supplying the external ballast. this current is the ballast inrush current. 4 inrush current is seen more like steps of 600 ma peak. th e startup of the regulator happens in steps of 50 mv in ~25 steps to reach ~1.2 v v dd_lv . each step peak current is within 600 ma table 22. voltage regulator electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 58 figure 9. low voltage monitor vs. reset 4.9 low voltage domain power consumption table 24 provides dc electrical characteristic s for significant application modes. th ese values are indi cative values; actual consumption depends on the application. table 23. low voltage monitor electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max v porup sr p supply for functional por module ? 1.0 ? 5.5 v v porh cc p power-on reset threshold ? 1.5 ? 2.6 v lv d h v 3 h cc t lvdhv3 low voltage detector high threshold ? 2.7 ? 2.85 v lv d h v 3 l cc t lvdhv3 low voltage detector low threshold ? 2.6 ? 2.74 v lv d h v 5 h cc t lvdhv5 low voltage detector high threshold ? 4.3 ? 4.5 v lv d h v 5 l cc t lvdhv5 low voltage detector low threshold ? 4.2 ? 4.4 v lvd lv c o r l cc p lvdlvcor low voltage detector low threshold t a = 25 c, after trimming 1.14 3 3 the min. and max variation across process voltage and temp erature will be available after device characterization. expected to be within 10 mv. v lvdlvbkpl cc p lvdlvbkp low voltage detector low threshold 1.14 3 v ddhv/lv v lvdhvxh/lvxh reset v lv d h v x l / lv x l
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 59 table 24. low voltage power domain electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified all temperatures are based on an ambient temperature. value unit min typ 2 2 target typical current consumption for the following typi cal operating conditions and configuration. process = typical, voltage = 1.2 v. max 3 3 target maximum current consumption for mode observed under typical operating conditions. process = fast, voltage = 1.32 v. i ddmax 4 4 running consumption is given on voltage regulator supply (v ddreg ). it does not include consumption linked to i/os toggling. this value is highly dependent on the application. the given value is t hought to be a worst case value with all cores and peripherals running, and code fetched from co de flash while modify operation on-going on data flash. it is to be noticed that this value can be significantly re duced by application: switch-off not used peripherals (default), reduce peripheral frequency through internal prescaler, fetch from ram most used functions, use low power mode when possible. cc d run mode maximum average current ? ? 210 300 5,6 5 higher current may sunk by device during power-up and standby exit. please refer to in rush current in ta b l e 2 2 . 6 maximum ?allowed? current is package dependent. ma i ddrun cc t run mode typical average current 7 7 only for the ?p? classification: code fetched from ram: se rial ips can and lin in loop back mode, dspi as master, pll as system clock (4 x multiplier) peripherals on (emi os/ctu/adc) and running at max frequency, periodic sw/wdg timer reset enabled. run current measured with typical application with accesses on both code flash and ram. at 120 mhz t a = 25 c ? 175 8,9 8 subject to change, configuration: 1 ? e200z4d + 4 kbit/s cache, 1 ? edma (32 ch), 4 ? flexcan (2 ? 500 kbit/s, 2 ? 125 kbit/s), 10 ? linflexd (20 kbit/s), 8 ? dspi (4 ? 2 mbit/s, 3 ? 4mbit/s, 1 ? 10 mbit/s), 40 ? pwm (200 hz), 40 ? adc input, 1 ? ctu (40 ch.), 1 ? flexray (2 ch., 10 mbit/s), 1 ? rtc, 4 ? pit, 1 ? swt, 1 ? stm. ethernet and e200z0h disabled. also reduced timed i/o channels for smaller packages. run current measured with typical application with accesses on both code flash and ram. 240 9,10 ma tat 80mhzt a = 25 c 110 8 150 10 ma i ddhalt cc p halt mode current 11 ? ? 25 35 ma i ddstop cc p stop mode current 12 no clocks active t a = 25 c ? 400 9 1200 9,13 a pt a = 150 c ? 10 9 30 9 ma i ddstdby3 (96 kb ram retained) cc p standby3 mode current 14 no clocks active t a = 25 c ? 60 175 a pt a = 150 c ? 1000 3000 a i ddstdby2 (64 kb ram retained) cc p standby2 mode current 15 no clocks active t a = 25 c ? 45 135 a pt a = 150 c ? 800 2000 a i ddstdby1 (8 kb ram retained) cc t standby1 mode current 16 no clocks active t a = 25 c ? 25 75 a pt a = 150 c ? 500 1000 a adders in lp mode cc t 32 khz osc ? t a =25c ? ? 5 a 4?40 mhz osc ? t a =25c ? ? 3 ma 16 mhz irc ? t a =25c ? ? 500 a 128 khz irc ? t a =25c ? ? 5 a
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 60 4.10 flash memory electrical characteristics 4.10.1 program/erase characteristics table 25 shows the code flash memory program and erase characteristics. 9 this value is obtained from limited sample set 10 subject to change, configuration: 1 ? e200z4d + 4 kbit/s cache, 1 ? e200z0h (1/2 system frequency), cse, 1 ? e dma (10 ch.), 6 ? flexcan (4 ? 500 kbit/s, 2 ? 125 kbit/s), 4 ? linflexd (20 kbit/s), 6 ? dspi (2 ? 2mbit/s, 3 ? 4mbit/s, 1 ? 10 mbit/s), 16 ? timed i/o, 16 ? adc input, 1 ? flexray (2 ch., 10 mbit/s), 1 ? fec (100 mbit/s), 1 ? rtc, 4 ? pit, 1 ? swt, 1 ? stm. for lower pin count packages reduc e the amount of timed i/o?s and adc channels. run current measured with typical applic ation with accesses on both code flash and ram. 11 data flash power down. code flash in low power. sirc 128 khz and firc 16 mhz on. 16 mhz xtal clock. flexcan: instances: 0, 1, 2 on (clocked but no reception or transmission), instances: 4, 5, 6 clocks gated. linflex: instances: 0, 1, 2 on (clocked but no reception or transmi ssion), instance: 3-9 clocks gated. emios: instance: 0 on (16 channels on pa[0]-pa[11] and pc[12]-pc[15]) wit h pwm 20 khz, instance: 1 clock gated. dspi: instance: 0 (clocked but no communication, instance: 1-7 clocks gated). rtc/api on. pit on. stm on. adc on but no conversion except 2 analog watchdogs. 12 only for the ?p? classification: no clock, firc 16 mhz off, sirc128 khz on, pll off, hpvreg off, lpvreg on. all possible peripherals off and clock gated. flash in power down mode. 13 this current is the maximum value at room temperat ure for any sample. the condition is same as note 11. 14 only for the ?p? classification: lpreg on, hpvreg off, 96 kb ram on, device configured for minimum consumption, all possible modules switched-off. 15 only for the ?p? classification: lpreg on, hpvreg off, 64 kb ram on, device configured for minimum consumption, all possible modules switched-off. 16 lpreg on, hpvreg off, 8 kb ram on, device config ured for minimum consumption, all possible modules switched off. table 25. code flash memory?program and erase specifications symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t dwprogram cc c double word (64 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?1850500s t 16kpperase 16 kb block pre-program and erase time ? 200 500 5000 ms t 32kpperase 32 kb block pre-program and erase time ? 300 600 5000 ms t 128kpperase 128 kb block pre-program and erase time ? 600 1300 5000 ms t eslat d erase suspend latency ? ? 30 30 s t esrt c erase suspend request rate 20 ? ? ? ms t pabt d program abort latency ? ? 10 10 s t eapt d erase abort latency ? ? 30 30 s
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 61 table 26 shows the data flash memory program and erase characteristics. table 26. data flash memory?program and erase specifications symbol c parameter value unit min typ 1 1 typical program and erase times assume nominal supply values and operation at 25 c. all times are subject to change pending device characterization. initial max 2 2 initial factory condition: < 100 program/erase cycles, 25 c, typical supply voltage. max 3 3 the maximum program and erase times occur after the spec ified number of program/erase cycles. these maximum values are characterized but not guaranteed. t wprogram cc c word (32 bits) program time 4 4 actual hardware programming times. this does not include software overhead. ?3070500s t 16kpperase 16 kb block pre-program and erase time ? 700 800 5000 ms t eslat d erase suspend latency ? ? 30 30 s t esrt c erase suspend request rate 10 ? ? ? ms t pabt d program abort latency ? ? 12 12 s t eapt d erase abort latency ? ? 30 30 s table 27. flash memory module life symbol c parameter conditions value unit min typ p/e cc c number of program/erase cycles per block for 16 kbyte blocks over the operating temperature range (t j ) ? 100,000 100,000 cycles number of program/erase cycles per block for 32 kbyte blocks over the operating temperature range (t j ) ? 10,000 100,000 cycles number of program/erase cycles per block for 128 kbyte blocks over the operating temperature range (t j ) ? 1,000 100,000 cycles retention cc c minimum data retention at 85 c average ambient temperature 1 1 ambient temperature averaged over dur ation of application, not to exceed recommended product operating temperature range. blocks with 0?1,000 p/e cycles 20 ? years blocks with 10,000 p/e cycles 10 ? years blocks with 100,000 p/e cycles 5?years
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 62 ecc circuitry provides correction of single bit faults and is us ed to improve further automotive reliability results. some unit s will experience single bit corrections throughout the life of the product with no impact to product reliability. 4.10.2 flash memory power supply dc characteristics table 29 shows the flash memory power supply dc characteristics on external supply. table 28. flash memory read access timing symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. max unit code flash memory data flash memory f read cc p maximum frequency for flash read ing 5 wait states 13 wait states 120 ? 2% mhz c 3 wait state 9 wait state 80 ? 2% d 3 wait states 2 2 wait states are subject to change per device characterization. ?64 ? 2% c ? 7 wait states table 29. flash memory power supply dc electrical characteristics symbol parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ?40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max i cfread 3 3 data based on characterization results, not tested in production. cc sum of the current consumption on v dd_hv_a on read access flash memory module read f cpu = 120 mhz ? 2% 4 4 f cpu 120 mhz ? 2% can be achieved over full temperature 125 c ambient, 150 c junction temperature. code flash memory 33 ma i dfread (3) data flash memory 13 i cfmod (3) cc sum of the current consumption on v dd_hv_a (program/erase) program/erase on-going while reading flash memory registers f cpu = 120 mhz ? 2% (4) code flash memory 52 ma i dfmod (3) data flash memory 13 i cflpw (3) cc sum of the current consumption on v dd_hv_a during flash memory low power mode code flash memory 1.1 ma i cfpwd (3) cc sum of the current consumption on v dd_hv_a during flash memory power down mode code flash memory 150 a i dfpwd (3) data flash memory 150
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 63 4.10.3 flash memory start-up/switch-off timings 4.11 electromagnetic compatib ility (emc) characteristics susceptibility tests are performed on a sa mple basis during produ ct characterization. 4.11.1 designing hardened software to avoid noise problems emc characterization and optimiza tion are performed at component level with a typical application environment and simplified mcu software. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user apply emc software optimization and pre-qualification tests in relation with the emc level requested for the application. ? software recommendations ?? the software flowchart must include the ma nagement of runaway conditions such as: ? corrupted program counter ? unexpected reset ? critical data corruption (control registers) ? pre-qualification trials ?? most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applied directly on the device. when unexpected behavior is detected, the software can be hardened to prev ent unrecoverable errors occurring. table 30. start-up time/switch-off time symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value unit min typ max t flarstexit cc d delay for flash memory module to exit reset mode code flash memory ? ? ? 125 s data flash memory ?? t flalpexit cc t delay for flash memory module to exit low-power mode code flash memory ???0.5 t flapdexit cc t delay for flash memory module to exit power-down mode code flash memory ???30 data flash memory ?? t flalpentry cc t delay for flash memory module to enter low-power mode code flash memory ???0.5
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 64 4.11.2 electromagnetic interference (emi) the product is monitored in terms of emission based on a typical application. this emission test conforms to the iec61967-1 standard, which specifies the general conditions for emi measurements. 4.11.3 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement me thods, the product is stressed in order to determine its performance in terms of electrical sensitivity. 4.11.3.1 electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) ar e applied to the pins of each sample accord ing to each pin combination. the sample size depends on th e number of supply pins in the device (3 parts ? (n+1) supply pin). this test conforms to the aec- q100-002/-003/-011 standard. table 31. emi radiated emission measurement 1,2 1 emi testing and i/o port waveforms per iec 61967-1, -2, -4. 2 for information on conducted emission and susceptibility measurement (norm iec 61967-4), please contact your local marketing representative. symbol c parameter conditions value unit min typ max ? sr ? scan range ? 0.150 1000 mhz f cpu sr ? operating frequency ? ? 120 ? mhz v dd_lv sr ? lv operating voltages ? ? 1.28 ? v s emi cc t peak level v dd = 5v, t a =25c, lqfp176 package test conforming to iec 61967-2, f osc = 40 mhz/f cpu = 120 mhz no pll frequency modulation ? ? 18 dbv 2% pll frequency modulation ??14 3 3 all values need to be confirmed during device validation. dbv table 32. esd absolute maximum ratings 1,2 1 all esd testing is in conformity with cdf-aec-q100 stre ss test qualification for au tomotive grade integrated circuits. 2 a device will be defined as a failure if after exposure to esd pulses the device no longer meets the device specification requirements. complete dc parametric and f unctional testing shall be performed per applicable device specification at room temperature followed by ho t temperature, unless specified otherwise in the device specification. symbol ratings conditions class max value 3 3 data based on characterization results, not tested in production. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = 25 c conforming to aec-q100-002 h1c 2000 v v esd(mm) electrostatic discharge voltage (machine model) t a = 25 c conforming to aec-q100-003 m2 200 v esd(cdm) electrostatic discharge voltage (charged device model) t a = 25 c conforming to aec-q100-011 c3a 500 750 (corners)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 65 4.11.3.2 static latch-up (lu) two complementary static tests are required on six parts to assess the latch-up performance: ? a supply over-voltage is appl ied to each power supply pin. ? a current injection is applied to each input, output and configurable i/o pin. these tests are compliant with the eia/jesd 78 ic latch-up standard. 4.12 fast external crystal o scillator (4?40 mhz) electrical characteristics the device provides an oscillator/resonator driver. figure 10 describes a simple model of the internal oscillat or driver and provides an example of a connection for an oscillator or a resonator. table 34 provides the parameter description of 4 mhz to 40 mhz crystals used for the design simulations. figure 10. crystal oscillator and resonator connection scheme note xtal/extal must not be directly used to drive external circuits. table 33. latch-up results symbol parameter conditions class lu static latch-up class t a = 125 c conforming to jesd 78 ii level a c2 c1 crystal xtal extal resonator xtal extal device device device extal xtal i r v dd r d
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 66 figure 11. fast external crystal oscillator (4 to 40 mhz) electrical characteristics table 34. crystal description nominal frequency (mhz) ndk crystal reference crystal equivalent series resistance esr ? crystal motional capacitance (c m ) ff crystal motional inductance (l m ) mh load on xtalin/xtalout c1 = c2 (pf) 1 1 the values specified for c1 and c2 are the same as used in simulations. it should be ensured that the testing includes all the parasitics (from the board, probe, crystal, et c.) as the ac / transient behavior depends upon them. shunt capacitance between xtalout and xtalin c0 2 (pf) 2 the value of c0 specified here includes 2 pf additional capacitance for parasitics (to be seen with bond-pads, package, etc.). 4 nx8045gb 300 2.68 591.0 21 2.93 8 nx5032ga 3002.46160.717 3.01 10 150 2.93 86.6 15 2.91 12 120 3.11 56.5 15 2.93 16 120 3.90 25.3 10 3.00 40 nx5032ga 50 6.18 2.56 8 3.49 table 35. fast external crystal oscillator (4 to 40 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f fxosc sr ? fast external crystal oscillator frequency ? 4.0 ? 40.0 mhz g mfxosc cc c fast external crystal oscillator transconductance v dd = 3.3 v 10% 8.699 13.159 15.846 ma/v v dd = 5.0 v 10% 9.440 13.159 16.859 v fxoscop t mxoscsu v xtal v fxosc valid internal clock 90% 10% 1/f mxosc s_mtrans bit (me_gs register) 1 0
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 67 4.13 slow external crystal oscillator (32 khz) electrical characteristics the device provides a low power oscillator/resonator driver. v fxosc cc t oscillation amplitude at extal f osc = 40 mhz for both v dd = 3.3 v 10%, v dd = 5.0 v 10% ?0.95 ? v v fxoscop cc p oscillation operating point ??1.8 v i fxosc ,3 cc t fast external crystal oscillator consumption v dd = 3.3 v 10%, f osc = 40 mhz ?2 2.2 ma v dd = 5.0 v 10%, f osc = 40 mhz ?2.3 2.5 v dd = 3.3 v 10%, f osc = 16 mhz ?1.3 1.5 v dd = 5.0 v 10%, f osc = 16 mhz ?1.6 1.8 t fxoscsu cc t fast external crystal oscillator start-up time f osc = 40 mhz for both v dd = 3.3 v 10%, v dd = 5.0 v 10% ?? 5 ms v ih sr p input high level cmos (schmitt trigger) oscillator bypass mode 0.65v dd_hv_a ?v dd_hv_a +0.4 v v il sr p input low level cmos (schmitt trigger) oscillator bypass mode ? 0.3 ? 0.35v dd_hv_a v 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 stated values take into account only analog module cons umption but not the digital contributor (clock tree and enabled peripherals). table 35. fast external crystal oscillator (4 to 40 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 68 figure 12. crystal oscillator and resonator connection scheme note osc32k_xtal/osc32k_extal must not be dir ectly used to drive external circuits. l figure 13. equivalent circuit of a quartz crystal table 36. crystal motional characteristics 1 symbol parameter conditions value unit min typ max l m motional inductance ? ? 11.796 ? kh c m motional capacitance ? ? 2 ? ff c1/c2 load capacitance at osc32k_xtal and osc32k_extal with respect to ground 2 ?18?28pf r m 3 motional resistance ac coupled @ c0 = 2.85 pf 4 ??65k ? ac coupled @ c0 = 4.9 pf (4) ??50 ac coupled @ c0 = 7.0 pf (4) ??35 ac coupled @ c0 = 9.0 pf (4) ??30 osc32k_xtal osc32k_extal device c2 c1 crystal osc32k_xtal osc32k_extal r p resonator device c0 c2 c1 c2 r m c1 l m c m crystal
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 69 figure 14. slow external crystal oscillator (32 khz) electrical characteristics 1 the crystal used is epson toyocom mc306. 2 this is the recommended range of load capacitance at osc32k_xtal and osc32k_extal with respect to ground. it includes all the parasitics due to board traces, crystal and package. 3 maximum esr (r m ) of the crystal is 50 k ?? 4 c0 includes a parasitic capacitance of 2.0 pf between osc32k_xtal and osc32k_extal pins. table 37. slow external crystal oscillator (32 khz) electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f sxosc sr ? slow external crystal oscillator frequency ? 32 32.768 40 khz g msxosc cc ? slow external crystal oscillator transconductance v dd = 3.3 v 10%, 17.45 ? 28.23 a/v v dd = 5.0 v 10% 17.79 ? 29.91 v sxosc cc t oscillation amplitude ? 1.2 1.4 1.7 v i sxoscbias cc t oscillation bias current ? 1.2 ? 4.4 a i sxosc cc t slow external crystal oscillator consumption ???7a t sxoscsu cc t slow external crystal oscillator start-up time ???2 3 3 start-up time has been measured with epson toyocom mc3 06 crystal. variation may be seen with other crystal. s oscon bit (osc_ctl register) t lpxosc32ksu 1 v osc32k_xtal v lpxosc32k valid internal clock 90% 10% 1/f lpxosc32k 0
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 70 4.14 fmpll electrical characteristics the device provides a frequency-modulated phase-locked loop (fmp ll) module to generate a fast system clock from the main oscillator driver. 4.15 fast internal rc oscillator (16 mhz) electrical characteristics the device provides a 16 mhz main internal rc oscillator. this is used as the defa ult clock at the power-up of the device and can also be used as input to pll. table 38. fmpll electrical characteristics symbol c parameter conditions 1 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. value 2 2 all values need to be confirmed during device validation. unit min typ max f pllin sr ? fmpll reference clock 3 3 pllin clock retrieved directly from 4-40 mhz xosc or 16 mirc. input characteristics are granted when oscillator is used in functional mode. when bypass mode is used, oscillator input clock should verify f pllin and ? pllin . ?4?64mhz ? pllin sr ? fmpll reference clock duty cycle (3) ?40?60% f pllout cc p fmpll output clock frequency ?16?120mhz f cpu sr ? system clock frequency ? ? ? 120 + 2% 4 4 f cpu 120 + 2% mhz can be achieved at 125 c. mhz f free cc p free-running frequency ? 20 ? 150 mhz t lock cc p fmpll lock time stable oscillator (f pllin = 16 mhz) 40 100 s ? t ltjit cc ? fmpll long term jitter f pllin = 40 mhz (resonator) , f pllclk @ 120 mhz, 4000 cycles ?? 6 (for < 1ppm) ns i pll cc c fmpll consumption t a = 25 c ? ? 3 ma table 39. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f firc cc p fast internal rc oscillator high frequency t a = 25 c, trimmed ? 16 ? mhz sr ? ? 12 20 i fircrun 3, cc t fast internal rc oscillator high frequency current in running mode t a = 25 c, trimmed ? ? 200 a i fircpwd cc d fast internal rc oscillator high frequency current in power down mode t a = 25 c ? ? 100 na dt a = 55 c ? ? 200 na dt a = 125 c ? ? 1 a
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 71 4.16 slow internal rc oscillator (128 khz) electrical characteristics the device provides a 128 khz low power internal rc oscillator. this can be used as the reference clock for the rtc module. i fircstop cc t fast internal rc oscillator high frequency and system clock current in stop mode t a = 25 c sysclk = off ? 500 ? a sysclk = 2 mhz ? 600 ? sysclk = 4 mhz ? 700 ? sysclk = 8 mhz ? 900 ? sysclk = 16 mhz ? 1250 ? t fircsu cc c fast internal rc oscillator start-up time t a = 55 c v dd = 5.0 v 10% ? ? 2.0 s ?v dd = 3.3 v 10% ? ? 5 ?t a = 125 c v dd = 5.0 v 10% ? ? 2.0 ?v dd = 3.3 v 10% ? ? 5 ? fircpre cc c fast internal rc oscillator precision after software trimming of f firc t a = 25 c ? 1?+1% ? firctrim cc c fast internal rc oscillator trimming step t a = 25 c ? 1.6 % ? fircvar cc c fast internal rc oscillator variation over temperature and supply with respect to f firc at t a = 25 c in high-frequency configuration ? ? 5?+5% 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 40. slow internal rc oscillator (128 khz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max f sirc cc p slow internal rc oscillator low frequency t a = 25 c, trimmed ? 128 ? khz sr ? ? 100 ? 150 i sirc 3, cc c slow internal rc oscillator low frequency current t a = 25 c, trimmed ? ? 5 a t sircsu cc p slow internal rc oscillator start-up time t a = 25 c, v dd = 5.0 v 10% ? 8 12 s table 39. fast internal rc oscillator (16 mhz) electrical characteristics symbol c parameter conditions 1 value 2 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 72 4.17 adc electrical characteristics 4.17.1 introduction the device provides two successive appr oximation register (sar) analog-to-digital convert ers (10-bit and 12-bit). note due to adc limitations, the two adcs cannot sample a shared channel at the same time i.e., their sampling windows cannot overlap if a shared channel is selected. if this is done, neither of the adcs can guarant ee their conversion accuracies. ? sircpre cc c slow internal rc oscillator precision after software trimming of f sirc t a = 25 c ? 2?+2% ? sirctrim cc c slow internal rc oscillator trimming step ??2.7? ? sircvar cc c slow internal rc oscillator variation in temperature and supply with respect to f sirc at t a = 55 c in high frequency configuration high frequency configuration ? 10 ? +10 % 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 all values need to be confirmed during device validation. 3 this does not include consumption linked to clock tree toggling and peripherals consumption when rc oscillator is on. table 40. slow internal rc oscillator (128 khz) electrical characteristics (continued) symbol c parameter conditions 1 value 2 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 73 figure 15. adc_0 characteristic and error definitions 4.17.1.1 input impedance and adc accuracy in the following analysis, the input circuit corres ponding to the precise ch annels is considered. to preserve the accuracy of the a/d converter, it is necessary that analog input pins have low ac impedance. placing a capacito r with good high frequency characteristics at the input pin of th e device can be effective: the capacitor should be as large as possible, ideally infinite. this capacitor contributes to attenuat ing the noise present on the input pin; furthermore, it sourc es charge during the sampling phase, when the anal og signal source is a high-impedance source. a real filter can typically be obtained by using a series re sistance with a capacitor on the input pin (simple rc filter). the rc filtering may be limited according to the value of source impedance of the tr ansducer or circuit supp lying the analog signal to be measured. the filter at the input pins mu st be designed taking into account the d ynamic characteristics of the input signal (bandwidth) and the equivalent input impedance of the adc itself. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 1023 1022 1021 1020 1019 1018 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 1017 1018 1019 1020 1021 1022 1023 1 lsb ideal = v dd_adc / 1024
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 74 in fact a current sink contri butor is represented by the charge shari ng effects with the sampling capacitance: c s being substantially a switched capacitance, with a frequency equal to the conversion rate of the adc, it can be seen as a resistive p ath to ground. for instance, assuming a conversion rate of 1 mhz, with c s equal to 3 pf, a resistance of 330 k ? is obtained (r eq = 1 / (fc ? c s ), where fc represents the conversion rate at the consider ed channel). to minimize the error induced by the voltage partitioning between this resistance (sampled voltage on c s ) and the sum of r s + r f + r l + r sw + r ad , the external circuit must be designed to respect the equation 4 : eqn. 4 equation 4 generates a constraint for external network design, in pa rticular on resistive path. in ternal switch resistances (r sw and r ad ) can be neglected with respect to external resistances. figure 16. input equivalent circuit (precise channels) figure 17. input equivalent circuit (extended channels) v a r s r f r l r sw r ad +++ + r eq --------------------------------------------------------------------------- ? 1 2 -- -lsb ? r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw1 channel selection switch impedance r ad sampling switch impedance c p pin capacitance (two contributions, c p1 and c p2 ) c s sampling capacitance c p1 r ad channel selection v a r f c f r s r l r sw1 c p3 c s v dd sampling source filter current limiter external circuit internal circuit scheme r s source impedance r f filter resistance c f filter capacitance r l current limiter resistance r sw channel selection switch impedance (two contributions r sw1 and r sw2 ) r ad sampling switch impedance c p pin capacitance (three contributions, c p1 , c p2 and c p3 ) c s sampling capacitance c p1 r ad channel selection v a c p2 extended r sw2 switch
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 75 a second aspect involving the capacitance network sha ll be considered. assuming the three capacitances c f , c p1 and c p2 are initially charged at the source voltage v a (refer to the equivalent circuit reported in figure 16 ): a charge sharing phenomenon is installed when the sampling phase is started (a/d switch close). figure 18. transient behavior during sampling phase in particular two different transient periods can be distinguished: 1. a first and quick charge transfer from the internal capacitance c p1 and c p2 to the sampling capacitance c s occurs (c s is supposed initially completely discharged): considering a worst case (since the time constant in reality would be faster) in which c p2 is reported in parallel to c p1 (call c p = c p1 + c p2 ), the two capacitances c p and c s are in series, and the time constant is eqn. 5 equation 5 can again be simplifi ed considering only c s as an additional worst condition. in reality, the transient is faster, but the a/d converter circuitry has been designed to be robust also in the very worst case: the sampling time t s is always much longer than the internal time constant: eqn. 6 the charge of c p1 and c p2 is redistributed also on c s , determining a new value of the voltage v a1 on the capacitance according to equation 7 : eqn. 7 2. a second charge transfer involves also c f (that is typically bigger than the on- chip capacitance) through the resistance r l : again considering the worst case in which c p2 and c s were in parallel to c p1 (since the time constant in reality would be faster), the time constant is: eqn. 8 in this case, the time constant depends on the external circuit: in particular imposing that the transient is completed well before the end of sampling time t s , a constraints on r l sizing is obtained: v a v a1 v a2 t t s v cs voltage transient on c s ? v < ? 0.5 lsb ? 1 2 ? 1 < (r sw + r ad ) c s << t s ? 2 = r l (c s + c p1 + c p2 ) ? 1 r sw r ad + ?? = c p c s ? c p c s + --------------------- ? ? 1 r sw r ad + ?? ? c s t s ? ? ?? ? v a c p1 c p2 + ?? ? = ? 2 r l ? c s c p1 c p2 ++ ?? ?
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 76 eqn. 9 of course, r l shall be sized also according to the current limitation constr aints, in combination with r s (source impedance) and r f (filter resistance). being c f definitively bigger than c p1 , c p2 and c s , then the final voltage v a2 (at the end of the charge transfer tr ansient) will be mu ch higher than v a1 . equation 10 must be respected (charge balance assuming now c s already charged at v a1 ): eqn. 10 the two transients above are not influenced by th e voltage source that, due to the presence of the r f c f filter, is not able to provide the extra charge to comp ensate the voltage drop on c s with respect to the ideal source v a ; the time constant r f c f of the filter is very high with respect to the sampling time (t s ). the filter is ty pically designed to act as anti-aliasing. figure 19. spectral representation of input signal calling f 0 the bandwidth of the source signal (and as a conseque nce the cut-off frequency of the anti-aliasing filter, f f ), according to the nyquist theorem the conversion rate f c must be at least 2f 0 ; it means that the constant ti me of the filter is greater than or at least equal to twice the conversion period (t c ). again the conversion period t c is longer than the sampling time t s , which is just a portion of it, even when fixed channel continu ous conversion mode is selected (fastest conversion rate at a specific channel): in conclusion it is evident that the time constant of the filter r f c f is definitively much higher than the sampling time t s , so the charge level on c s cannot be modified by the analog signal source during the time in which the sampling switch is closed. the considerations above lead to impose new constraints on the external circuit, to reduce the accur acy error due to the voltag e drop on c s ; from the two charge balance equations above, it is simple to derive equation 11 between the ideal and real sampled voltage on c s : eqn. 11 10 ? 2 ? 10 r l c s c p1 c p2 ++ ?? ? ? =t s ? v a2 c s c p1 c p2 c f +++ ?? ? v a c f ? v a1 +c p1 c p2 +c s + ?? ? = f 0 f analog source bandwidth (v a ) f 0 f sampled signal spectrum (f c = conversion rate) f c f anti-aliasing filter (f f = rc filter pole) f f 2 f 0 < f c (nyquist) f f = f 0 (anti-aliasing filtering condition) t c < 2 r f c f (conversion rate vs. filter pole) noise v a v a2 ----------- - c p1 c p2 +c f + c p1 c p2 +c f c s ++ ------------------------------------------------------- - =
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 77 from this formula, in the worst case (when v a is maximum, that is for instance 5 v ), assuming to accept a maximum error of half a count, a constraint is evident on c f value: adc_0 (10-bit) eqn. 12 adc_1 (12-bit) eqn. 13 4.17.1.2 adc electrical characteristics note all adc conversion characteristics described in the table below are applicable only for the precision channels. the data for semi-precision and extended channels is awaited and same will be subsequently updated in later revs. table 41. adc input leakage current symbol c parameter conditions value unit min typ max i lkg cc c input leakage current t a = ? 40 c no current injection on adjacent pin ? 1 ? na ct a = 25 c ? 1 ? ct a = 105 c ? 8 200 pt a = 125 c ? 45 400 table 42. adc conversion char acteristics (10-bit adc_0) symbol c parameter conditions 1 value unit min typ max v ss_adc0 sr ? voltage on vss_hv_adc0 (adc_0 reference) pin with respect to ground (v ss_hv ) 2 ? ? 0.1 ? 0.1 v v dd_adc0 sr ? voltage on vdd_hv_adc0 pin (adc_0 reference) with respect to ground (v ss_hv ) ?v dd_hv_a ? 0.1 ? v dd_hv_a +0.1 v v ainx sr ? analog input voltage 3 ?v ss_adc0 ? 0.1 ? v dd_adc0 +0.1 v f adc0 sr ? adc_0 analog frequency ? 6? 32 + 2% mhz t adc0_pu sr ? adc_0 power up delay ? ?? 1.5 s c f 2048 c s ? ? c f 8192 c s ? ?
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 78 t adc0_s cc t sample time 4 f adc = 32 mhz 0.125 ? s f adc = 30 mhz 0.150 t adc0_c cc p conversion time 5,6 f adc = 32 mhz 0.625 ? s f adc = 30 mhz 0.700 ? c s cc d adc_0 input sampling capacitance ??? 3 pf c p1 cc d adc_0 input pin capacitance 1 ??? 3 pf c p2 cc d adc_0 input pin capacitance 2 ??? 1 pf c p3 cc d adc_0 input pin capacitance 3 ??? 1 pf r sw1 cc d internal resistance of analog source ??? 3 k ? r sw2 cc d internal resistance of analog source ? ? ? 2 k ? r ad cc d internal resistance of analog source ??? 2 k ? i inj sr ? input current injection current injection on one adc_0 input, different from the converted one v dd = 3.3 v 10% ? 5? 5 ma v dd = 5.0 v 10% ? 5 ? 5 | inl | cc t absolute value for integral non-linearity no overload ? 0.5 1.5 lsb | dnl | cc t absolute differential non-linearity no overload ? 0.5 1.0 lsb | ofs | cc t absolute offset error ? ? 0.5 ? lsb | gne | cc t absolute gain error ?? 0.6 ? lsb tuep cc p total unadjusted error 7 for precise channels, input only pins without current injection ? 2 0.6 2 lsb t with current injection ? 3 3 tuex cc t total unadjusted error (7) for extended channel without current injection ? 3 1 3 lsb t with current injection ? 4 4 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 analog and digital v ss_hv must be common (to be tied together externally). table 42. adc conversion characteristics (10-bit adc_0) (continued) symbol c parameter conditions 1 value unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 79 figure 20. adc_1 characteristic and error definitions 3 v ainx may exceed v ss_adc0 and v dd_adc0 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0x3ff. 4 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the capacitance to reach its final voltage level within t adc0_s . after the end of the sample time t adc0_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc0_s depend on programming. 5 conversion time = bit evaluation time + sampling time + 1 clock cycle delay. 6 refer to adc conversion table for detailed calculations. 7 total unadjusted error: the maximum error that occurs with out adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. (2) (1) (3) (4) (5) offset error ose offset error ose gain error ge 1 lsb (ideal) v in(a) (lsb ideal ) (1) example of an actual transfer curve (2) the ideal transfer curve (3) differential non-linearity error (dnl) (4) integral non-linearity error (inl) (5) center of a step of the actual transfer curve code out 4095 4094 4093 4092 4091 4090 5 4 3 2 1 0 7 6 1 2 3 4 5 6 7 4090 4091 4092 4093 4094 4095 1 lsb ideal = avdd / 4096
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 80 note all adc conversion characteristics described in the table below are applicable only for the precision channels. the data for semi-precision and extended channels is awaited and same will be subsequently updated in later revs. table 43. conversion characteristics (12-bit adc_1) symbol parameter conditions 1 value unit min typ max v ss_adc1 sr voltage on vss_hv_adc1 (adc_1 reference) pin with respect to ground (v ss_hv ) 2 ? ? 0.1 0.1 v v dd_adc1 3 sr voltage on vdd_hv_adc1 pin (adc_1 reference) with respect to ground (v ss_hv ) ?v dd_hv_a ? 0.1 v dd_hv_a +0.1 v v ainx 3,4 sr analog input voltage 5 ?v ss_adc1 ? 0.1 v dd_adc1 +0.1 v f adc1 sr adc_1 analog frequency ? 8 + 2% 32 + 2% mhz t adc1_pu sr adc_1 power up delay ? 1.5 s t adc1_s cc sample time 6 vdd=5.0 v ? 440 ns sample time (6) vdd=3.3 v ?530 t adc1_c cc conversion time 7, 8 vdd=5.0 v f adc1 = 32 mhz 2 s conversion time (7), (6) vdd =5.0 v f adc 1 = 30 mhz 2.1 conversion time (7), (6) vdd=3.3 v f adc 1 = 20 mhz 3 conversion time (7), (6) vdd =3.3 v f adc1 = 15 mhz 3.01 c s cc adc_1 input sampling capacitance ?5 pf c p1 cc adc_1 input pin capacitance 1 ?3 pf
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 81 c p2 cc adc_1 input pin capacitance 2 ?1 pf c p3 cc adc_1 input pin capacitance 3 ?1.5 pf r sw1 cc internal resistance of analog source ?1 k ? r sw2 cc internal resistance of analog source ?2 k ? r ad cc internal resistance of analog source ?0.3 k ? i inj sr input current injection current injection on one adc_1 input, different from the converted one v dd = 3.3 v 10% ? 5 ? 5 ma v dd = 5.0 v 10% ? 5 ? 5 inlp cc absolute integral non-linearity-preci se channels no overload 1 3 lsb inlx cc absolute integral non-linearity-exten ded channels no overload 1.5 5 lsb dnl cc absolute differential non-linearity no overload 0.5 1 lsb ofs cc absolute offset error ?2 lsb gne cc absolute gain error ?2 lsb tuep 9 cc total unadjusted error for precise channels, input only pins without current injection ? 6 6 with current injection ? 8 8 tuex (9) cc total unadjusted error for extended channel without current injection ? 10 10 lsb with current injection ? 12 12 lsb 1 v dd = 3.3 v 10% / 5.0 v 10%, t a = ? 40 to 125 c, unless otherwise specified. 2 analog and digital v ss_hv must be common (to be tied together externally). table 43. conversion characteristics (12-bit adc_1) (continued) symbol parameter conditions 1 value unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 82 4.18 fast ethernet controller mii signals use cmos signal levels compatible with devices ope rating at 3.3 v. signals are not ttl compatible. they follow the cmos electrical characteristics. 4.18.1 mii receive signal timing (rxd [3:0], rx_dv, rx_er, and rx_clk) the receiver functions correctly up to a rx_clk maximum frequency of 25 mhz + 1%. there is no minimum frequency requirement. in addition, the system clock frequency must exceed four times the rx _clk frequency in 2:1 mode and two times the rx_clk frequency in 1:1 mode. 3 pa3, pa7, pa10, pa11 and pe12 adc_1 channels are coming from v dd_hv_b domain hence vdd_hv_adc1 should be within 100 mv of vdd_hv_b wh en these channels are used for adc_1. 4 vdd_hv_adc1 can operate at 5v condition while v dd_hv_b can operate at 3.3v prov ided that adc_1 channels coming from v dd_hv_b domain are limited in max swing as v dd_hv_b . 5 v ainx may exceed v ss_adc1 and v dd_adc1 limits, remaining on absolute maximum ratings, but the results of the conversion will be clamped respectively to 0x000 or 0xfff. 6 during the sample time the input capacitance c s can be charged/discharged by the external source. the internal resistance of the analog source must allow the c apacitance to reach its final voltage level within t adc1_s . after the end of the sample time t adc1_s , changes of the analog input voltage have no effect on the conversion result. values for the sample clock t adc1_s depend on programming. 7 conversion time = bit ev aluation time + sampling ti me + 1 clock cycle delay. 8 refer to adc conversion table for detailed calculations. 9 total unadjusted error: the maximum error that occurs wit hout adjusting offset and gain errors. this error is a combination of offset, gain and integral linearity errors. table 44. mii receive signal timing spec characteristic min max unit m1 rxd[3:0], rx_dv, rx_er to rx_clk setup 5?ns m2 rx_clk to rxd[3:0], rx_dv, rx_er hold 5?ns m3 rx_clk pulse width high 35% 65% rx_clk period m4 rx_clk pulse width low 35% 65% rx_clk period
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 83 figure 21. mii receive signal timing diagram 4.18.2 mii transmit signal timing (t xd[3:0], tx_en, tx_er, tx_clk) the transmitter functions correctly up to a tx_clk maximu m frequency of 25 mhz +1%. there is no minimum frequency requirement. in addition, the system cloc k frequency must exceed four times the tx_c lk frequency in 2:1 mode and two times the tx_clk frequency in 1:1 mode. the transmit outputs (txd[3:0], tx_en, tx_er) can be programme d to transition from either the rising or falling edge of tx_clk, and the timing is the same in either case. this options allows the use of non-compliant mii phys. refer to the fast ethernet controller (f ec) chapter of the jpc5604b reference manual for details of this option and how to enable it. table 45. mii transmit signal timing 1 1 output pads configured with sre = 0b11. spec characteristic min max unit m5 tx_clk to txd[3:0], tx_en, tx_er invalid 5?ns m6 tx_clk to txd[3:0], tx_en, tx_er valid ?25ns m7 tx_clk pulse width high 35% 65% tx_clk period m8 tx_clk pulse width low 35% 65% tx_clk period m1 m2 rx_clk (input) rxd[3:0] (inputs) rx_dv rx_er m3 m4
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 84 figure 22. mii transmit signal timing diagram 4.18.3 mii async inputs sign al timing (crs and col) figure 23. mii async inputs timing diagram 4.18.4 mii serial management ch annel timing (mdio and mdc) the fec functions correctly with a maximum mdc frequency of 2.5 mhz. table 46. mii async inputs signal timing 1 1 output pads configured with sre = 0b11. spec characteristic min max unit m9 crs, col minimum pulse width 1.5 ? tx_clk period table 47. mii serial management channel timing 1 spec characteristic min max unit m10 mdc falling edge to mdio output invalid (minimum propagation delay) 0?ns m11 mdc falling edge to mdio output valid (max prop delay) ?25ns m12 mdio (input) to mdc rising edge setup 28 ? ns m13 mdio (input) to mdc rising edge hold 0?ns m6 tx_clk (input) txd[3:0] (outputs) tx_en tx_er m5 m7 m8 crs, col m9
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 85 figure 24. mii serial management channel timing diagram m14 mdc pulse width high 40% 60% mdc period m15 mdc pulse width low 40% 60% mdc period 1 output pads configured with sre = 0b11. table 47. mii serial management channel timing 1 (continued) spec characteristic min max unit m11 mdc (output) mdio (output) m12 m13 mdio (input) m10 m14 m15
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 86 4.19 on-chip peripherals 4.19.1 current consumption table 48. on-chip peripherals current consumption 1 symbol c parameter conditions value 2 unit min typ max i dd_hv_a(can) cc d can (flexcan) supply current on v dd_hv_a 500 kbps total (static + dynamic) consumption: flexcan in loop-back mode xtal@8 mhz used as can engine clock source message sending period is 580 s 7.652 ? f periph + 84.73 a 125 kbps 8.0743 ? f periph + 26.757 i dd_hv_a(emios) cc d emios supply current on v dd_hv_a static consumption: emios channel off global prescaler enabled 28.7 ? f periph dynamic consumption: it does not change varying the frequency (0.003 ma) 3 i dd_hv_a(sci) cc d sci (linflex) supply current on v dd_hv_a total (static + dynamic) consumption: lin mode baudrate: 20 kbps 4.7804 ? f periph + 30.946 i dd_hv_a(spi) cc d spi (dspi) supply current on v dd_hv_a ballast static consumption (only clocked) 1 ballast dynamic consumption (continuous communication): baudrate: 2 mbit trasmission every 8 s frame: 16 bits 16.3 ? f periph
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 87 i dd_hv_a(adc) cc d adc supply current on v dd_hv_a v dd = 5.5 v ballast static consumption (no conversion) 0.0409 ? f periph ma v dd = 5.5 v ballast dynamic consumption (continuous conversion) 0.0049 ? f periph i dd_hv_adc(adc) cc d adc supply current on v dd_hv_adc v dd = 5.5 v analog static consumption (no conversion) 0.0017 ? f periph v dd = 5.5 v analog dynamic consumption (continuous conversion) 0.075 ? f periph + 0.032 i dd_hv(flash) cc d cflash + dflash supply current on v dd_hv_adc v dd = 5.5 v ? 13.25 i dd_hv(pll) cc d pll supply current on v dd_hv v dd = 5.5 v ? 0.0031 ? f periph 1 operating conditions: t a = 25 c, f periph = 8 mhz to 120 mhz. 2 f periph is in absolute value. table 48. on-chip peripherals current consumption 1 symbol c parameter conditions value 2 unit min typ max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 88 4.19.2 dspi characteristics table 49. dspi timing spec characteristic symbol unit min max 1 dspi cycle time t sck refer note 1 ?ns ? internal delay between pad associated to sck and pad associated to csn in master mode for csn1->0 ? t csc ? 115 ns ? internal delay between pad associated to sck and pad associated to csn in master mode for csn1->1 ? t asc 15 ? ns 2 cs to sck delay 2 t csc 7?ns 3 after sck delay 3 t asc 15 ? ns 4 sck duty cycle t sdc 0.4 ? t sck 0.6 ? t sck ns ?slave setup time (ss active to sck setup time) t suss 5?ns ? slave hold time (ss active to sck hold time) t hss 10 ? ns 5 slave access time (ss active to sout valid) 4 t a ? 42 ns 6 slave sout disable time (ss inactive to sout high-z or invalid) t dis ? 25 ns 7 csx to pcss time t pcsc 0?ns 8pcss to pcsx time t pasc 0?ns
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 89 9 data setup time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 5 master (mtfe = 1, cpha = 1) t sui 36 5 36 36 ? ? ? ? ns ns ns ns 10 data hold time for inputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) 5 master (mtfe = 1, cpha = 1) t hi 0 4 0 0 ? ? ? ? ns ns ns ns 11 data valid (after sck edge) master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t suo ? ? ? ? 12 37 12 12 ns ns ns ns 12 data hold time for outputs master (mtfe = 0) slave master (mtfe = 1, cpha = 0) master (mtfe = 1, cpha = 1) t ho 0 6 9.5 0 7 0 8 ? ? ? ? ns ns ns ns 1 this value of this parameter is dependent upon the external device delays and the other parameters mentioned in this table. 2 the maximum value is programmable in dspi_ctar n [pssck] and dspi_ctar n [cssck]. for jpc5604b, the spec value of t csc will be attained only if t dspi x pssck x cssck > ? t csc . 3 the maximum value is programmable in dspi_ctar n [pasc] and dspi_ctar n [asc]. for jpc5604b, the spec value of t asc will be attained only if t dspi x pasc x asc > ? t asc. 4 the parameter value is obtained from t suss and t suo for slave. 5 this number is calculated assuming the sm pl_pt bitfield in dspi_mcr is set to 0b00. 6 for dspi1, the data hold time fo r outputs in master (mtfe = 0) is ? 2 ns. 7 for dspi1, the data hold time for outputs in master (mtfe = 1, cpha = 0) is ? 2 n. 8 for dspi1, the data hold time for outputs in master (mtfe = 1, cpha = 1) is ? 2 ns. table 49. dspi timing (continued) spec characteristic symbol unit min max
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 90 figure 25. dspi classic spi timing?master, cpha = 0 figure 26. dspi classic spi timing?master, cpha = 1 data last data first data first data data last data sin sout csx sck output 4 9 12 1 11 10 4 sck output (cpol = 0) (cpol = 1) 3 2 note: numbers shown reference ta b l e 4 9 . data last data first data sin sout 12 11 10 last data data first data sck output sck output csx 9 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 91 figure 27. dspi classic spi timing?slave, cpha = 0 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 12 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 92 figure 28. dspi classic spi timing?slave, cpha = 1 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 93 figure 29. dspi modified transfer format timing?master, cpha = 0 csx 3 1 4 10 4 9 12 11 sck output sck output sin sout first data data last data first data data last data 2 (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 94 figure 30. dspi modified transfer format timing?master, cpha = 1 csx 10 9 12 11 sck output sck output sin sout first data data last data first data data last data (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 95 figure 31. dspi modified transfer format timing?slave, cpha = 0 figure 32. dspi modified transfer format timing?slave, cpha = 1 last data first data 3 4 1 data data sin sout ss 4 5 6 9 11 10 sck input first data last data sck input 2 (cpol = 0) (cpol = 1) 12 note: numbers shown reference ta b l e 4 9 . 5 6 9 12 11 10 last data last data sin sout ss first data first data data data sck input sck input (cpol = 0) (cpol = 1) note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 96 figure 33. dspi pcs strobe (pcss ) timing 4.19.3 nexus characteristics table 50. nexus debug port timing 1 1 jtag specifications in this table apply when used for debug functionality. all nexus timing relative to mcko is measured from 50% of mcko and 50% of the respective signal. nexus timing specified at v dde =4.0?5.5v, t a =t l to t h , and c l = 30 pf with src = 0b11. spec characteristic symbol min max unit 1 mcko cycle time 2 2 mcko can run up to 1/2 of full system frequency. it can also run at system frequency when it is <60 mhz. t mcyc 16.3 ? ns 2 mcko duty cycle t mdc 40 60 % 3 mcko low to mdo, mseo , evto data valid 3 3 mdo, mseo , and evto data is held valid until next mcko low cycle. t mdov ?0.1 0.25 t mcyc 4 evti pulse width t evtipw 4.0 ? t tcyc 5 evto pulse width t evtopw 1t mcyc 6 tck cycle time 4 4 the system clock frequency needs to be three times faster than the tck frequency. t tcyc 40 ? ns 7 tck duty cycle t tdc 40 60 % 8 tdi, tms data setup time t ntdis, t ntmss 8?ns 9 tdi, tms data hold time t ntdih, t ntmsh 5?ns 10 tck low to tdo data valid t jov 025ns csx 7 8 pcss note: numbers shown reference ta bl e 4 9 .
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 97 figure 34. nexus output timing 1 2 mcko mdo mseo evto output data valid 3 evti 4 5
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 98 figure 35. nexus tdi, tms, tdo timing 4.19.4 jtag characteristics table 51. jtag characteristics no. symbol c parameter value unit min typ max 1t jcyc cc d tck cycle time 64 ? ? ns 2t tdis cc d tdi setup time 10 ? ? ns 3t tdih cc d tdi hold time 5 ? ? ns 4t tmss cc d tms setup time 10 ? ? ns 5t tmsh cc d tms hold time 5 ? ? ns tdo 8 9 tms, tdi 10 tck 6 7
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 99 figure 36. timing diagram - jtag boundary scan 6t tdov cc d tck low to tdo valid ? ? 33 ns 7t tdoi cc d tck low to tdo invalid 6 ? ? ns ?t tdc cc d tck duty cycle 40 ? 60 % ?t tckrise cc d tck rise and fall times ? ? 3 ns table 51. jtag characteristics (continued) no. symbol c parameter value unit min typ max input data valid output data valid data inputs data outputs data outputs tck note: numbers shown reference ta bl e 5 1 . 3/5 2/4 7 6
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 100 5 package characteristics 5.1 package mechanical data 5.1.1 176 lqfp package mechanical drawing
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 101 figure 37. 176 lqfp mechanical drawing (part 1 of 3)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 102 figure 38. 176 lqfp mechanical drawing (part 2 of 3)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 103 figure 39. 176 lqfp mechanical drawing (part 3 of 3) 5.1.2 208 lqfp package mechanical drawing e e
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 104 figure 40. 208 lqfp mechanical drawing (part 1 of 3)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 105 figure 41. 208 lqfp mechanical drawing (part 2 of 3)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 106 figure 42. 208 lqfp mechanical drawing (part 3 of 3)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 107
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 108 5.1.3 256 mapbga package mechanical drawing figure 43. 256 mapbga mechanical drawing (part 1 of 2)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 109 figure 44. 256 mapbga mechanical drawing (part 2 of 2)
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 110 6 ordering information figure 45. commercial product code structure qualification status power architecture automotive platform core version flash size (core dependent) product optional fields mpc56 c f0 ll example code: 46 temperature spec. package code qualification status m = mc status s = auto qualified p = pc status pc = power architecture automotive platform 56 = power architecture in 90 nm core version 4 = e200z4d core version (highest core version in the case of multiple cores) flash memory size 4 = 1.5 mb 5 = 2 mb 6 = 3 mb product version b = body c = gateway optional fields c = cse module available blank = none of these options available fab and mask version indicator f = atmc 0 = first version of the mask temperature spec. c = ?40 c to 85 c v = ?40 c to 105 c m = ?40 c to 125 c r = tape & reel (blank if tray) r package code lu = 176 lqfp lt = 208 lqfp mj = 256 mapbga cpu frequency 1 = e200z4d operates up to 120 mhz 8 = e200z4d operates up to 80 mhz shipping method r = tape and reel blank = tray 1 cpu frequency fab and mask indicator m b
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 111 7 revision history table 52 summarizes revisions to this document. table 52. revision history revision date changes 1 15 april 2010 initial release 2 17 aug 2010 ? editing and formatting updates throughout the document. ? updated voltage regulator capacitance connection figure . ? added a new sub-section ?v dd_bv options? ? program and erase specifications: -updated tdwprogram typ to 22 us -updated t128kpperase max to 5000 ms -added t esus parameter ? added 208 mapbga thermal characteristics ? added recommendation in the voltage regulator electrical characteristics section. ? added crystal description table in fast external crystal oscillator (4 to 140 mhz) electrical characteristics section and co rrected the cross-reference to the same. ? added new sections - pad types, system pins and functional ports ? updated typ numbers in the flash program and erase specifications table ? added a new table: program and erase specifications (data flash) ? flash read access timing table: added data flash memory numbers ? flash power supply dc electrical characteristics table: updated idfread and idfmod values for data flas h, removed idflpw parameter ? updated feature list. ? family comparison table: updated adc channels and added adc footnotes. ? block diagram: updated adc channels and added legends. ? series block summary: added new blocks. ? functional port pin descriptions table: added osc32k_xtal and osc32k_extal function at pb8 and pb9 port pins. ? electrical characteristics: replaced vss with vss_hv thro ughout the section. ? absolute maximum ratings, recommended operating conditions (3.3 v) and recommended operating conditions (5.0 v) tables: vrc_ctrl min is updated to "0". ? recommended operating conditions (3.3 v) and recommended operating conditions (5.0 v) tables: clarified vi n parameter, clarified footnote 2 in both tables. ? lqfp thermal characteristics sectio n: updated numbers for lqfp packages. ? low voltage power domain electrical characteristics table: clarified footnotes based upon review comments. ? code flash memory?program and erase specifications: updated tesrt to 20 ms. ? adc electrical characteristics section: replace adc0 with adc_0 and adc1 with adc_1 throughout the document. ? dspi characteristics section: replaced pcsx with csx in all figures and tables.
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 112 3 tbd ? replaced vil min from ?0.4 v to ?0.3 v in the following tables: - i/o input dc electrical characteristics - reset electrical characteristics - fast external crystal oscillator (4 to 40 mhz) electrical characteristics ? updated crystal oscillator and resonator connection scheme figure ? specified npn transistor as the recommended bcp68 transistor throughout the document ? code and data flash memory?program and erase specifications tables: renamed the parameter t esus to t eslat ? revised the footnotes in the ?functional port pin descriptions? table. ? in the ?system pin descriptions? table, added a footnote to the a pads regarding not using ibe. for ports pb[12?15], changed anx to adc0_x. ? revised the presentation of the adc functions on the following ports: pb[4?7] pd[0?11] ? adc conversion characteristics (10-bit adc_0) table and conversion characteristics (12-bit adc_1) table- up dated footnote 5 and 7 respectively for the definition of the conversion time. ? data flash memory?program and erase specifications: updated t wprogram to 500 s and t 16kpperase to 500 s. corrected teslat cl asssification from ?c? to ?d?. ? code flash memory?program and erase specifications: corrected teslat classification from ?c? to ?d?. ? flash start-up time/switch-off time: changed t flarstexit classification from ?c? to ?d?. ? functional port pin description: added a footnote at the pb [9] port pin. ? absolute maximum ratings table: added footnote 1. ? low voltage power domain electrical characteristics table: updated iddhalt, iddstop, iddstby3, iddstdby2, iddstdby1. ? slow external crystal oscillator (32 khz) electrical characteristics table: updated g msxosc , v sxosc , i sxoscbias and i sxosc. ? fmpll electrical characteristics table: updated ? t lt j i t. ? fast internal rc oscillator (16 mhz) el ectrical characteristics table: updated tfircsu and ifircpwd. ? mii serial management channel timing table: updated m12 ? jtag characteristics table: updated t tdov. ? low voltage monitor electrical characteristics table: updated vlvdhv3h, vlvdhv3l, vlvdhv5h, vlvdhv5l. ? dspi electricals table: updated spec 1, 5, 6. updated footnote 2 and 3. added ? t csc , ? t asc , t suss , t hss. ? io consumption table: updated all parameter values. ? dspi electricals: updated ? t csc max to 115 ns. ? low voltage power domain electrical characteristics table: added footnote 9. ? adc electrical characteristics: added 2 notes above 10-bit and 12-bit conversion tables. table 52. revision history (continued) revision date changes
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 113 appendix a abbreviations table 53 lists abbreviations used but not defined elsewhere in this document. table 53. abbreviations abbreviation meaning cs chip select evto event out mcko message clock out mdo message data out mseo message start/end out mtfe modified timing format enable sck serial communications clock sout serial data out tbd to be defined tck test clock input tdi test data input tdo test data output tms test mode select
mpc5646c microcontroller data sheet, rev. 3 preliminary?subject to change without notice freescale semiconductor 114 how to reach us: home page: www.freescale.com e-mail: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com document number: mpc5646c rev. 3 may 2011 information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freesc ale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2010, 2011. all rights reserved.

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